mainboard/aopen: Use C89 comments style & remove commented code

Change-Id: I0014fc030888d71f7951c97bccc7cef0e1c45186
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

5 files changed, 46 insertions, 45 deletions

diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c
index e6ae815a4c..e2f4c23877 100644
--- a/src/mainboard/aopen/dxplplusu/acpi_tables.c
+++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c
@@ -32,37 +32,37 @@ unsigned long acpi_fill_madt(unsigned long current)
 	device_t dev = 0;
 	struct resource* res = NULL;
 
-	// SJM: Hard-code CPU LAPIC entries for now
+	/* SJM: Hard-code CPU LAPIC entries for now */
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
 
-	// Southbridge IOAPIC
+	/* Southbridge IOAPIC */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
-	// P64H2 Bus B IOAPIC
+	/* P64H2 Bus B IOAPIC */
 	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();		/* Config.lb error? */
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
-	// P64H2 Bus A IOAPIC
+	/* P64H2 Bus A IOAPIC */
 	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
-		BUG();		// Config.lb error?
+		BUG();		/* Config.lb error? */
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 
-	// Map ISA IRQ 0 to IRQ 2
+	/* Map ISA IRQ 0 to IRQ 2 */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
 
-	// IRQ9 differs from ISA standard - ours is active high, level-triggered
+	/* IRQ9 differs from ISA standard - ours is active high, level-triggered */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
 
 	return current;
diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h
index 96321c9fc4..965b8b78b0 100644
--- a/src/mainboard/aopen/dxplplusu/bus.h
+++ b/src/mainboard/aopen/dxplplusu/bus.h
@@ -16,23 +16,24 @@
 #ifndef DXPLPLUSU_BUS_H_INCLUDED
 #define DXPLPLUSU_BUS_H_INCLUDED
 
-// These were determined by seeing how coreboot enumerates the various
-// PCI (and PCI-like) buses on the board.
+/* These were determined by seeing how coreboot enumerates the various
+ * PCI (and PCI-like) buses on the board.
+ */
 
 #define PCI_BUS_ROOT		0
-#define PCI_BUS_AGP		1	// AGP
-#define PCI_BUS_E7501_HI_B	2	// P64H2#1
-#define PCI_BUS_P64H2_B		3	// P64H2#1 bus B
-#define PCI_BUS_P64H2_A		4	// P64H2#1 bus A
-#define PCI_BUS_ICH4		5	// ICH4
+#define PCI_BUS_AGP		1	/* AGP */
+#define PCI_BUS_E7501_HI_B	2	/* P64H2#1 */
+#define PCI_BUS_P64H2_B		3	/* P64H2#1 bus B */
+#define PCI_BUS_P64H2_A		4	/* P64H2#1 bus A */
+#define PCI_BUS_ICH4		5	/* ICH4 */
 
-// IOAPIC addresses determined by coreboot enumeration.
-// Someday add functions to get APIC IDs and versions from the chips themselves.
+/* IOAPIC addresses determined by coreboot enumeration. */
+/* Someday add functions to get APIC IDs and versions from the chips themselves. */
 
 #define IOAPIC_ICH4		2
-#define IOAPIC_P64H2_BUS_B	3	// IOAPIC 3 at 02:1c.0  MBAR = fe300000 DataAddr = fe300010
-#define IOAPIC_P64H2_BUS_A	4	// IOAPIC 4 at 02:1e.0  MBAR = fe301000 DataAddr = fe301010
+#define IOAPIC_P64H2_BUS_B	3	/* IOAPIC 3 at 02:1c.0  MBAR = fe300000 DataAddr = fe300010 */
+#define IOAPIC_P64H2_BUS_A	4	/* IOAPIC 4 at 02:1e.0  MBAR = fe301000 DataAddr = fe301010 */
 
-#define INTEL_IOAPIC_NUM_INTERRUPTS 	24	// Both ICH-4 and P64-H2
+#define INTEL_IOAPIC_NUM_INTERRUPTS 	24	/* Both ICH-4 and P64-H2 */
 
 #endif
diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c
index cfeb2e2980..418d547ca3 100644
--- a/src/mainboard/aopen/dxplplusu/fadt.c
+++ b/src/mainboard/aopen/dxplplusu/fadt.c
@@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->pm1_evt_len = 4;
 	fadt->pm1_cnt_len = 2;
-	// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+	/* XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) */
 	fadt->pm2_cnt_len = 0;
 	fadt->pm_tmr_len = 4;
 	fadt->gpe0_blk_len = 8;
diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c
index 9619f290d9..8d9298b6f3 100644
--- a/src/mainboard/aopen/dxplplusu/irq_tables.c
+++ b/src/mainboard/aopen/dxplplusu/irq_tables.c
@@ -31,37 +31,37 @@
 static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,
 	PIRQ_VERSION,
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,		// Size of this struct in bytes
-	0,			 			// PCI bus number on which the interrupt router resides
-	PCI_DEVFN(31, 0),   				// PCI device/function number of the interrupt router
-	0,		 				// PCI-exclusive IRQ bitmap
-	PCI_VENDOR_ID_INTEL,				// Vendor ID of compatible PCI interrupt router
-	PCI_DEVICE_ID_INTEL_82801DB_LPC,		// Device ID of compatible PCI interrupt router
-	0,		 				// Additional miniport information
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 		// Reserved, must be zero
-	0xB1,      					// Checksum of the entire structure (causes 8-bit sum == 0)
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,		/* Size of this struct in bytes */
+	0,			 			/* PCI bus number on which the interrupt router resides */
+	PCI_DEVFN(31, 0),   				/* PCI device/function number of the interrupt router */
+	0,		 				/* PCI-exclusive IRQ bitmap */
+	PCI_VENDOR_ID_INTEL,				/* Vendor ID of compatible PCI interrupt router */
+	PCI_DEVICE_ID_INTEL_82801DB_LPC,		/* Device ID of compatible PCI interrupt router */
+	0,		 				/* Additional miniport information */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 		/* Reserved, must be zero */
+	0xB1,      					/* Checksum of the entire structure (causes 8-bit sum == 0) */
 	{
-		// NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
-		//		 This was determined from linux-2.6.11/arch/i386/pci/irq.c
-		// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
-		// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
-		// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
+		/* NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space */
+		/*		 This was determined from linux-2.6.11/arch/i386/pci/irq.c */
+		/* bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 */
+		/* ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 */
+		/* Not sure why IRQ9 isn't routable (inherited from Tyan S2735) */
 
-		//				   	  INTA#              INTB#	      INTC#             INTD#
-		//  bus,		device #  	  {link  , bitmap}, {link  , bitmap}, {link  , bitmap}, {link  , bitmap},  slot, rfu
+		/*				   	  INTA#              INTB#	      INTC#             INTD# */
+		/*  bus,		device #  	  {link  , bitmap}, {link  , bitmap}, {link  , bitmap}, {link  , bitmap},  slot, rfu */
 
-		{PCI_BUS_ROOT,		PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// IDE / SMBus
-		{PCI_BUS_ROOT,		PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}},   0, 0},	// USB 1.1
+		{PCI_BUS_ROOT,		PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	/* IDE / SMBus */
+		{PCI_BUS_ROOT,		PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}},   0, 0},	/* USB 1.1 */
 
 		{PCI_BUS_P64H2_B,	PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},
 		{PCI_BUS_P64H2_B,	PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},
-		{PCI_BUS_P64H2_B,	PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},    // GbE
+		{PCI_BUS_P64H2_B,	PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},    /* GbE */
 
 		{PCI_BUS_P64H2_A,	PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},
 		{PCI_BUS_P64H2_A,	PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},
-		{PCI_BUS_P64H2_A,	PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},    // SCSI
+		{PCI_BUS_P64H2_A,	PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}},   0, 0},    /* SCSI */
 
-		{PCI_BUS_ICH4,		PCI_DEVFN(3, 0),  {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}},  0, 0},	// 32-bit slot
+		{PCI_BUS_ICH4,		PCI_DEVFN(3, 0),  {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}},  0, 0},	/* 32-bit slot */
 
 	}
 };
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
index 5e7a15958a..3fba1ad860 100644
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ b/src/mainboard/aopen/dxplplusu/romstage.c
@@ -46,14 +46,14 @@ void mainboard_romstage_entry(unsigned long bist)
 		},
 	};
 
-	// Get the serial port running and print a welcome banner
+	/* Get the serial port running and print a welcome banner */
 	lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
-	// Halt if there was a built in self test failure
+	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	// If this is a warm boot, some initialization can be skipped
+	/* If this is a warm boot, some initialization can be skipped */
 	if (!e7505_mch_is_ready()) {
 		enable_smbus();