diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-25 11:55:28 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 18:23:01 +0000 |
| commit | 4af2342673befb65b19363c9265a0887ff001eec (patch) | |
| tree | 0b3b99788a79588712cfc44be4e0202542e8796f /src/mainboard | |
| parent | 67c2a7b487bfaea90303faa5e8ef9e33c3000f1c (diff) | |
| download | coreboot-4af2342673befb65b19363c9265a0887ff001eec.tar.xz | |
google/kahlee: Move DRAM clear override to devicetree
Kahlee needs to keep its DRAM contents after a reset. Move this
override out of the OemCustomize.c file to a devicetree register
setting.
Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/kahlee/OemCustomize.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/kahlee/devicetree.cb | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index bbb51e49dc..36bb419d41 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -35,6 +35,4 @@ void OemPostParams(AMD_POST_PARAMS *PostParams) { PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; - /* disable memory clear for pstore memory storage and boot time */ - PostParams->MemConfig.EnableMemClr = FALSE; } diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb index 4376011797..c4535225e2 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb @@ -18,6 +18,7 @@ chip soc/amd/stoneyridge { { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" device cpu_cluster 0 on device lapic 10 on end |