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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-06 10:32:12 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-27 15:53:25 +0000 |
| commit | 4b2d865820a0025818933fa13360d170b5281dff (patch) | |
| tree | 04361fac512e68137b4850e78508f4d9bf33d3ae /src/mainboard | |
| parent | 5d4cf36044a2cfa13d72688e8f0592be31760785 (diff) | |
| download | coreboot-4b2d865820a0025818933fa13360d170b5281dff.tar.xz | |
mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functions
Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index f5222ed0a4..ddbb97ca6d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -120,23 +120,9 @@ static const u8 spd_addr[] = { #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) -/* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - static void write_GPIO(void) { - pnp_enter_ext_func_mode(GPIO1_DEV); + pnp_enter_conf_state(GPIO1_DEV); pnp_set_logical_device(GPIO1_DEV); pnp_write_config(GPIO1_DEV, 0x30, 0x01); pnp_write_config(GPIO1_DEV, 0x60, 0x00); @@ -147,9 +133,9 @@ static void write_GPIO(void) pnp_write_config(GPIO1_DEV, 0xf0, 0xff); pnp_write_config(GPIO1_DEV, 0xf1, 0xff); pnp_write_config(GPIO1_DEV, 0xf2, 0x00); - pnp_exit_ext_func_mode(GPIO1_DEV); + pnp_exit_conf_state(GPIO1_DEV); - pnp_enter_ext_func_mode(GPIO2_DEV); + pnp_enter_conf_state(GPIO2_DEV); pnp_set_logical_device(GPIO2_DEV); pnp_write_config(GPIO2_DEV, 0x30, 0x01); pnp_write_config(GPIO2_DEV, 0xf0, 0xef); @@ -159,16 +145,16 @@ static void write_GPIO(void) pnp_write_config(GPIO2_DEV, 0xf5, 0x48); pnp_write_config(GPIO2_DEV, 0xf6, 0x00); pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); - pnp_exit_ext_func_mode(GPIO2_DEV); + pnp_exit_conf_state(GPIO2_DEV); - pnp_enter_ext_func_mode(GPIO3_DEV); + pnp_enter_conf_state(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV); pnp_write_config(GPIO3_DEV, 0x30, 0x00); pnp_write_config(GPIO3_DEV, 0xf0, 0xff); pnp_write_config(GPIO3_DEV, 0xf1, 0xff); pnp_write_config(GPIO3_DEV, 0xf2, 0xff); pnp_write_config(GPIO3_DEV, 0xf3, 0x40); - pnp_exit_ext_func_mode(GPIO3_DEV); + pnp_exit_conf_state(GPIO3_DEV); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |