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| author | Shaunak Saha <shaunak.saha@intel.com> | 2020-06-15 23:59:52 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-15 08:40:37 +0000 |
| commit | 60e6f6e1e52a62556d3025f061c1a8edecdbc29f (patch) | |
| tree | 255b6df97fd75fb88545655ad031e3ba5ecc1c78 /src/mainboard | |
| parent | 1a8949c0c430f6caf7ab67b0ccbca6d3ead0d486 (diff) | |
| download | coreboot-60e6f6e1e52a62556d3025f061c1a8edecdbc29f.tar.xz | |
mb/google/volteer: Enable SATA Port Dito Config
Enable SataPortsEnableDitoConfig for port 1.
BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42415
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 18bfcc4ff7..f0bb25bfeb 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -110,6 +110,7 @@ chip soc/intel/tigerlake register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |