diff options
author | Felix Singer <felixsinger@posteo.net> | 2021-01-06 03:54:47 +0000 |
---|---|---|
committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-19 10:11:09 +0000 |
commit | 7dc57159fe819acb9280522528fb68f3e9befacc (patch) | |
tree | 788fbb3bdc345098940edecfb89277bd6b4908e8 /src/mainboard | |
parent | 8434d92c305b2c04a61e42cbb2882a829cfb4f67 (diff) | |
download | coreboot-7dc57159fe819acb9280522528fb68f3e9befacc.tar.xz |
mb/clevo/kbl-u: Move memory init config to variant level
Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.
Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/clevo/kbl-u/Makefile.inc | 2 | ||||
-rw-r--r-- | src/mainboard/clevo/kbl-u/include/variant/romstage.h | 8 | ||||
-rw-r--r-- | src/mainboard/clevo/kbl-u/romstage.c | 32 | ||||
-rw-r--r-- | src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c | 38 |
4 files changed, 50 insertions, 30 deletions
diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc index b424d4da19..99dd1cdc17 100644 --- a/src/mainboard/clevo/kbl-u/Makefile.inc +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -5,6 +5,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c + ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/clevo/kbl-u/include/variant/romstage.h b/src/mainboard/clevo/kbl-u/include/variant/romstage.h new file mode 100644 index 0000000000..cfcc6ab08d --- /dev/null +++ b/src/mainboard/clevo/kbl-u/include/variant/romstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c index a39117e2f3..3976116534 100644 --- a/src/mainboard/clevo/kbl-u/romstage.c +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -1,37 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/romstage.h> -#include <spd_bin.h> -#include <string.h> - -static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - const u16 RcompResistor[3] = {121, 81, 100}; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} +#include <variant/romstage.h> void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - - struct spd_block blk = { - .addr_map = {0x50, 0x52}, - }; - - get_spd_smbus(&blk); - dump_spd_info(&blk); - - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = TRUE; - mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + variant_configure_fspm(mupd); } diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c new file mode 100644 index 0000000000..4e9d57c21a --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <spd_bin.h> +#include <string.h> +#include <variant/romstage.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void variant_configure_fspm(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} |