diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-07-26 15:37:11 +0530 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:17:56 +0200 |
| commit | 89f6d6079ef88ff20c7da3422d1298d614ed6b5a (patch) | |
| tree | f2856afcff4ce1e104dcc16d75ceea1d7575a9b6 /src/mainboard | |
| parent | 50b9258a0bbe6cf99606c87a5b9b835ff0689a7d (diff) | |
| download | coreboot-89f6d6079ef88ff20c7da3422d1298d614ed6b5a.tar.xz | |
skylake/devicetree: Add LPC EC decode range
Define LPC decode ranges for EC communication.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error
Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15898
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/lars/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 3 |
4 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 384d374877..3f40449f0f 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -13,8 +13,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command range is in 0x800-0x8ff + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index ff145c548f..c315cd947d 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -13,8 +13,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command range is in 0x800-0x8ff + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 8ecacdd267..e411ad4a2b 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -12,8 +12,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command range is in 0x800-0x8ff + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 4aeb0b1467..07efd54e4c 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -12,8 +12,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command range is in 0x800-0x8ff + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" |