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authorAaron Durbin <adurbin@chromium.org>2017-04-19 10:02:27 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-24 22:03:13 +0200
commit9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a (patch)
tree8130661a121e39da3e0241a3760b0f57ad250824 /src/mainboard
parent8bc896f7129b8e47cbca1c15b87a449620186cf8 (diff)
downloadcoreboot-9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a.tar.xz
soc/intel/common: provide default tis_plat_irq_status() implementation
On Intel platforms utilizing the CR50 TPM the interrupts are routed to GPIOs connected to the GPE blocks. Therefore, provide a common implementation for tis_plat_irq_status() to reduce code duplication. This code could be further extended to not be added based on MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now. Change-Id: I955df0a536408b2ccd07146893337c53799e243f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19369 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
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