diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-04-14 14:08:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-16 06:44:36 +0000 |
| commit | a0d48096ad83813d959886ba354f7b7eb0aea179 (patch) | |
| tree | e29c99197a7b0b7131549233869c4ea72cb3479c /src/mainboard | |
| parent | 6935350ad6610fca943afc4ae96125760538f98c (diff) | |
| download | coreboot-a0d48096ad83813d959886ba354f7b7eb0aea179.tar.xz | |
mb/google/brya: Configure TCSS OC pins for brya
TCSS OC pins has not been correctly configured for brya.
This patch fills the value from devicetree to correct the OC pins
mapping
BUG=b:184653645
BRANCH=None
TEST=check if UPD value has been reflected correctly
Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index d7e2522c7e..4ef1da9bf9 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -47,6 +47,10 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, |