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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-06-04 13:43:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:40:16 +0000 |
| commit | aa5e8e099e83647cd6347bcbc82e2c11a6cac1d7 (patch) | |
| tree | 31fa45febdf749472325be5f00c57520bba40229 /src/mainboard | |
| parent | 37fedc0414af6e5e2daccef5caa4b37632699f15 (diff) | |
| download | coreboot-aa5e8e099e83647cd6347bcbc82e2c11a6cac1d7.tar.xz | |
siemens/mc_apl5: Change PTN interface settings
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index c0770f3124..f6fed97551 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -76,7 +76,8 @@ int ptn3460_init(const char *hwi_block) return (PTN_BUS_ERROR | status); /* Set up configuration data according to the hwinfo block we get. */ cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; + /* Drive LVDS clock for single mode on odd bus per default. */ + cfg.lvds_interface_ctrl1 = 0x01; if (disp_con == PF_DISPLCON_LVDS_DUAL) /* Turn on dual LVDS lane and clock. */ cfg.lvds_interface_ctrl1 |= 0x0b; |