diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-07 21:43:48 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-07 21:43:48 +0000 |
| commit | abf2ad716daff751d75907d47bcae4a7044fd7b4 (patch) | |
| tree | f82427b43d76a4791253373affed1af8669e2e7b /src/mainboard | |
| parent | 389240f288b2708617a35ebe8d7f89b3bff316c5 (diff) | |
| download | coreboot-abf2ad716daff751d75907d47bcae4a7044fd7b4.tar.xz | |
newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
237 files changed, 0 insertions, 46129 deletions
diff --git a/src/mainboard/a-trend/atc-6220/Config.lb b/src/mainboard/a-trend/atc-6220/Config.lb deleted file mode 100644 index da9f349ac2..0000000000 --- a/src/mainboard/a-trend/atc-6220/Config.lb +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/a-trend/atc-6220/Options.lb b/src/mainboard/a-trend/atc-6220/Options.lb deleted file mode 100644 index 68843932f1..0000000000 --- a/src/mainboard/a-trend/atc-6220/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/a-trend/atc-6240/Config.lb b/src/mainboard/a-trend/atc-6240/Config.lb deleted file mode 100644 index 1f8a889d27..0000000000 --- a/src/mainboard/a-trend/atc-6240/Config.lb +++ /dev/null @@ -1,142 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - io 0x60 = 0x00 - end - device pnp 3f0.7 on # Game port / MIDI / GPIO 1 - io 0x60 = 0x201 - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 3f0.8 off # GPIO 2 / WDT - end - device pnp 3f0.9 off # GPIO 3 - end - device pnp 3f0.a off # ACPI - end - device pnp 3f0.b off # HWM (TODO) - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - device pci c.0 on end # Onboard audio (ES1371) - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/a-trend/atc-6240/Options.lb b/src/mainboard/a-trend/atc-6240/Options.lb deleted file mode 100644 index 7930819f12..0000000000 --- a/src/mainboard/a-trend/atc-6240/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/abit/be6-ii_v2_0/Config.lb b/src/mainboard/abit/be6-ii_v2_0/Config.lb deleted file mode 100644 index 58193b8fe8..0000000000 --- a/src/mainboard/abit/be6-ii_v2_0/Config.lb +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 7.1 on end # IDE, UDMA/33 (part of 82371EB) - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - device pci 13.0 on end # IDE, UDMA/66 (HPT366 controller) - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/abit/be6-ii_v2_0/Options.lb b/src/mainboard/abit/be6-ii_v2_0/Options.lb deleted file mode 100644 index c415fd21d0..0000000000 --- a/src/mainboard/abit/be6-ii_v2_0/Options.lb +++ /dev/null @@ -1,98 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb. -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 9 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. -default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. - -end diff --git a/src/mainboard/advantech/pcm-5820/Config.lb b/src/mainboard/advantech/pcm-5820/Config.lb deleted file mode 100644 index 44ec55dec7..0000000000 --- a/src/mainboard/advantech/pcm-5820/Config.lb +++ /dev/null @@ -1,129 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/winbond/w83977f # SUper I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.4 on # RTC / On-Now control - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # IR - # TODO? - end - device pnp 3f0.7 on # GPIO 1 - # TODO? - end - device pnp 3f0.8 on # GPIO 2 - # TODO? - end - end - end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio (onboard) - device pci 12.4 on end # VGA - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end - chip cpu/amd/model_gx1 # CPU - end -end diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb deleted file mode 100644 index 684e4dce30..0000000000 --- a/src/mainboard/advantech/pcm-5820/Options.lb +++ /dev/null @@ -1,103 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_VIDEO_MB -uses CONFIG_SPLASH_GRAPHIC -uses CONFIG_GX1_VIDEO -uses CONFIG_GX1_VIDEOMODE -uses CONFIG_PIRQ_ROUTE - -## Enable VGA with a splash screen (only 640x480 to run on most monitors). -## We want to support up to 1024x768@16 so we need 2MiB video memory. -## Note: Higher resolutions might need faster SDRAM speed. -default CONFIG_GX1_VIDEO = 1 -default CONFIG_GX1_VIDEOMODE = 0 -default CONFIG_SPLASH_GRAPHIC = 1 -default CONFIG_VIDEO_MB = 2 - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 2 # Override this in targets/*/Config.lb. -default CONFIG_PIRQ_ROUTE = 1 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc " -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 - -end diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb deleted file mode 100644 index de229062f7..0000000000 --- a/src/mainboard/amd/db800/Config.lb +++ /dev/null @@ -1,152 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x0000105a" - register "lpc_serirq_polarity" = "0x0000EFA5" - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "1" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3F8" - register "com1_irq" = "4" - register "com2_enable" = "0" - register "com2_address" = "0x2F8" - register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci d.0 on end # Ethernet - device pci e.0 on end # Slot1 - device pci f.0 on # ISA Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off end # Com2 - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HW Monitor - end - end - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end -end - diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb deleted file mode 100644 index 5ec7b1ecdb..0000000000 --- a/src/mainboard/amd/db800/Options.lb +++ /dev/null @@ -1,180 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_VIDEO_MB=8 -default CONFIG_PCI_ROM_RUN=0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=4 -default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 32768 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb deleted file mode 100644 index fde48a1cc2..0000000000 --- a/src/mainboard/amd/dbm690t/Config.lb +++ /dev/null @@ -1,258 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -#The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/amd/dbm690t/Options.lb b/src/mainboard/amd/dbm690t/Options.lb deleted file mode 100644 index d5d54f985e..0000000000 --- a/src/mainboard/amd/dbm690t/Options.lb +++ /dev/null @@ -1,301 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VGA_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_VIDEO_MB -uses CONFIG_GFXUMA -uses CONFIG_HAVE_MAINBOARD_RESOURCES - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 - -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_VGA_ROM_RUN=1 - -# BTDC: Only one HT device on Herring. -#HT Unit ID offset -#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="dbm690t" -default CONFIG_MAINBOARD_VENDOR="amd" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_VIDEO_MB=1 -default CONFIG_GFXUMA=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -### End Options.lb -end diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb deleted file mode 100644 index 5f0dc33d7b..0000000000 --- a/src/mainboard/amd/norwich/Config.lb +++ /dev/null @@ -1,125 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - register "lpc_serirq_enable" = "0x00001002" - register "lpc_serirq_polarity" = "0x0000EFFD" - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "1" - register "com1_address" = "0x3F8" - register "com1_irq" = "4" - register "com2_enable" = "0" - register "com2_address" = "0x2F8" - register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci b.0 on end # Slot 3 - device pci c.0 on end # Slot 4 - device pci d.0 on end # Slot 1 - device pci e.0 on end # Slot 2 - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end -end - diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb deleted file mode 100644 index 0ca20260f2..0000000000 --- a/src/mainboard/amd/norwich/Options.lb +++ /dev/null @@ -1,180 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_VIDEO_MB=8 -default CONFIG_PCI_ROM_RUN=0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=6 -default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb deleted file mode 100644 index 1f59668328..0000000000 --- a/src/mainboard/amd/pistachio/Config.lb +++ /dev/null @@ -1,218 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -#The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_AM2 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge, K8 HT Configuration - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - # device pci 0.1 off end # CLK - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 off end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 off end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x438d - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.1 on end # K8 Address Map - device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode - device pci 18.3 on end # K8 Miscellaneous Control - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/amd/pistachio/Options.lb b/src/mainboard/amd/pistachio/Options.lb deleted file mode 100644 index 922edf5210..0000000000 --- a/src/mainboard/amd/pistachio/Options.lb +++ /dev/null @@ -1,301 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VGA_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_VIDEO_MB -uses CONFIG_GFXUMA -uses CONFIG_HAVE_MAINBOARD_RESOURCES - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 - -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_VGA_ROM_RUN=1 - -# BTDC: Only one HT device on Herring. -#HT Unit ID offset -#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="pistachio" -default CONFIG_MAINBOARD_VENDOR="amd" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_VIDEO_MB=1 -default CONFIG_GFXUMA=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -### End Options.lb -end diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb deleted file mode 100644 index 9083949f44..0000000000 --- a/src/mainboard/amd/rumba/Config.lb +++ /dev/null @@ -1,115 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/gx2 - device apic_cluster 0 on - chip cpu/amd/model_gx2 - device apic 0 on end - end - end - device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - register "lpc_serirq_enable" = "0x80" # enabled with default timing - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.4 on end # UHCI - end - end -end - diff --git a/src/mainboard/amd/rumba/Options.lb b/src/mainboard/amd/rumba/Options.lb deleted file mode 100644 index e6a9b48cad..0000000000 --- a/src/mainboard/amd/rumba/Options.lb +++ /dev/null @@ -1,159 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb deleted file mode 100644 index 1e2f1b2046..0000000000 --- a/src/mainboard/amd/serengeti_cheetah/Config.lb +++ /dev/null @@ -1,358 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE - object mptable.o -end - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - -#if CONFIG_GENERATE_ACPI_TABLES -# object acpi_tables.o -# object fadt.o -# if CONFIG_SB_HT_CHAIN_ON_BUS0 -# object dsdt_bus0.o -# else -# object dsdt.o -# end -# object ssdt.o -# if CONFIG_ACPI_SSDTX_NUM -# if CONFIG_SB_HT_CHAIN_ON_BUS0 -# object ssdt2_bus0.o -# else -# object ssdt2.o -# end -# end -#end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "mv dsdt_lb.hex dsdt.c" - end - object ./dsdt.o - - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - - if CONFIG_ACPI_SSDTX_NUM - makerule ssdt2.c - depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" - action "mv pci2.hex ssdt2.c" - end - object ./ssdt2.o - makerule ssdt3.c - depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" - action "mv pci3.hex ssdt3.c" - end - object ./ssdt3.o - makerule ssdt4.c - depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" - action "mv pci4.hex ssdt4.c" - end - object ./ssdt4.o - end -end - - if CONFIG_USE_INIT - # compile cache_as_ram.c to auto.o - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## - -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for amd/serengeti_cheetah -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-2-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-2-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-3-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-3-1 - device i2c 57 on end - end - end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - end # device pci 19.0 - - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - - - end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - -end - - diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb deleted file mode 100644 index a20289d794..0000000000 --- a/src/mainboard/amd/serengeti_cheetah/Options.lb +++ /dev/null @@ -1,325 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 -## extra SSDT num -default CONFIG_ACPI_SSDTX_NUM=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=8 -default CONFIG_MAX_PHYSICAL_CPUS=4 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x8 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0xa - -#real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - - -## -## for rev F training on AP purpose -## -default CONFIG_AP_CODE_IN_CAR=1 -default CONFIG_MEM_TRAIN_SEQ=1 -default CONFIG_WAIT_BEFORE_CPUS_INIT=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah" -default CONFIG_MAINBOARD_VENDOR="AMD" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb deleted file mode 100644 index da52d4d69a..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb +++ /dev/null @@ -1,362 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE - object mptable.o -end - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "mv dsdt_lb.hex dsdt.c" - end - object ./dsdt.o - - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - - if CONFIG_ACPI_SSDTX_NUM - makerule ssdt2.c - depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" - action "mv pci2.hex ssdt2.c" - end - object ./ssdt2.o - makerule ssdt3.c - depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" - action "mv pci3.hex ssdt3.c" - end - object ./ssdt3.o - makerule ssdt4.c - depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" - action "mv pci4.hex ssdt4.c" - end - object ./ssdt4.o - makerule ssdt5.c - depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" - action "mv pci5.hex ssdt5.c" - end - object ./ssdt5.o - end -end - - if CONFIG_USE_INIT - # compile cache_as_ram.c to auto.o - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## - -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -dir /southbridge/amd/amd8151 - -# sample config for amd/serengeti_cheetah_fam10 -chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F_1207 #L1 and DDR2 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - end - end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #pci_domain - #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end - -end - - diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb deleted file mode 100644 index 5a17e3449c..0000000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ /dev/null @@ -1,365 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_PCI_BUS_SEGN_BITS - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_AMDMCT - -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_AMD_UCODE_PATCH_FILE - -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - -## -## -#FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 1024K - 8K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 8k -default CONFIG_FAILOVER_SIZE=0x02000 - -#more 1M for pgtbl -#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. -default CONFIG_RAMTOP=16384*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 -## extra SSDT num -default CONFIG_ACPI_SSDTX_NUM=31 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## -default CONFIG_SMP=1 -default CONFIG_MAX_PHYSICAL_CPUS=8 -default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS -default CONFIG_LOGICAL_CPUS=1 - -#default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x00 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0xa - -#real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -#it only be 0, 1, 2, 3, 4 and default is 0 -#default CONFIG_PCI_BUS_SEGN_BITS=3 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc4000 -default CONFIG_DCACHE_RAM_SIZE=0x0c000 -#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 -default CONFIG_USE_INIT=0 - -#default CONFIG_AP_CODE_IN_CAR=1 -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 - -default CONFIG_AMDMCT = 1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10" -default CONFIG_MAINBOARD_VENDOR="AMD" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -## -## Set microcode patch file name -## -## Barcelona rev DR-Ax: "mc_patch_01000020.h" -## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h" -## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" -## Shanghai rev DA-C2: "mc_patch_0100009f.h" -## -default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 768k heap -## -default CONFIG_HEAP_SIZE=0xc0000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00200000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb deleted file mode 100644 index 13e351f7d7..0000000000 --- a/src/mainboard/arima/hdama/Config.lb +++ /dev/null @@ -1,297 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# config for arima/hdama -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on # PCIX bridge - ## On board NIC A - #chip drivers/generic/generic - # device pci 3.0 on - # irq 0 = 0x13 - # end - #end - ## On board NIC B - #chip drivers/generic/generic - # device pci 4.0 on - # irq 0 = 0x13 - # end - #end - ## PCI Slot 3 - #chip drivers/generic/generic - # device pci 1.0 on - # irq 0 = 0x11 - # irq 1 = 0x12 - # irq 2 = 0x13 - # irq 3 = 0x10 - # end - #end - ## PCI Slot 4 - #chip drivers/generic/generic - # device pci 2.0 on - # irq 0 = 0x12 - # irq 1 = 0x13 - # irq 2 = 0x10 - # irq 3 = 0x11 - # end - #end - end - device pci 0.1 on end # IOAPIC - device pci 1.0 on # PCIX bridge - ## PCI Slot 1 - #chip drivers/generic/generic - # device pci 1.0 on - # irq 0 = 0x11 - # irq 1 = 0x12 - # irq 2 = 0x13 - # irq 3 = 0x10 - # end - #end - ## PCI Slot 2 - #chip drivers/generic/generic - # device pci 2.0 on - # irq 0 = 0x12 - # irq 1 = 0x13 - # irq 2 = 0x10 - # irq 3 = 0x11 - # end - #end - end - device pci 1.1 on end # IOAPIC - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent of the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end # USB0 - device pci 0.1 on end # USB1 - device pci 0.2 off end # USB 2.0 - device pci 1.0 off end # LAN - device pci 6.0 on end # ATI Rage XL - ## PCI Slot 5 (correct?) - #chip drivers/generic/generic - # device pci 5.0 on - # irq 0 = 0x11 - # irq 1 = 0x12 - # irq 2 = 0x13 - # irq 3 = 0x10 - # end - #end - ## PCI Slot 6 (correct?) - #chip drivers/generic/generic - # device pci 4.0 on - # irq 0 = 0x10 - # irq 1 = 0x11 - # irq 2 = 0x12 - # irq 3 = 0x13 - # end - #end - - end - # LPC bridge - device pci 1.0 on - chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1.1 on end # IDE - device pci 1.2 on end # SMBus 2.0 - device pci 1.3 on # System Management - chip drivers/generic/generic - #phillips pca9545 smbus mux - device i2c 70 on - # analog_devices adm1026 - chip drivers/generic/generic - device i2c 2c on end - end - end - device i2c 70 on end - device i2c 70 on end - device i2c 70 on end - end - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end - device pci 1.5 off end # AC97 Audio - device pci 1.6 on end # AC97 Modem - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # chip northbridge/amd/amdk8 - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end -end - diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb deleted file mode 100644 index c047282de6..0000000000 --- a/src/mainboard/arima/hdama/Options.lb +++ /dev/null @@ -1,242 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_LOGICAL_CPUS -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_LOGICAL_CPUS enables dual core support -## -default CONFIG_LOGICAL_CPUS=1 - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -#VGA -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" -default CONFIG_MAINBOARD_VENDOR="ARIMA" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb deleted file mode 100644 index e3cc41b135..0000000000 --- a/src/mainboard/artecgroup/dbe61/Config.lb +++ /dev/null @@ -1,124 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - register "lpc_serirq_enable" = "0x00001002" - register "lpc_serirq_polarity" = "0x0000EFFD" - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x2F8" - register "com1_irq" = "3" - register "com2_enable" = "1" - register "com2_address" = "0x3F8" - register "com2_irq" = "4" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci b.0 on end # Slot 3 - device pci c.0 on end # Slot 4 - device pci d.0 on end # Slot 1 - device pci e.0 on end # Slot 2 - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end - -end - diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb deleted file mode 100644 index 3aebf7446c..0000000000 --- a/src/mainboard/artecgroup/dbe61/Options.lb +++ /dev/null @@ -1,180 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_VIDEO_MB=8 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=3 -default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/artecgroup/dbe61/realmode/Config.lb b/src/mainboard/artecgroup/dbe61/realmode/Config.lb deleted file mode 100644 index 899843db07..0000000000 --- a/src/mainboard/artecgroup/dbe61/realmode/Config.lb +++ /dev/null @@ -1,2 +0,0 @@ -config chip.h -driver vgabios.o diff --git a/src/mainboard/asi/mb_5blgp/Config.lb b/src/mainboard/asi/mb_5blgp/Config.lb deleted file mode 100644 index 7bd25dc188..0000000000 --- a/src/mainboard/asi/mb_5blgp/Config.lb +++ /dev/null @@ -1,128 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 on end # Ethernet - device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # System wake-up control (SWC) - irq 0x60 = 0x500 - end - device pnp 2e.5 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 on # GPIO - irq 0x60 = 0x800 - end - device pnp 2e.8 on # Fan speed control - irq 0x60 = 0x900 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "0" # No connector on this board - end - end - chip cpu/amd/model_gx1 # CPU - end -end diff --git a/src/mainboard/asi/mb_5blgp/Options.lb b/src/mainboard/asi/mb_5blgp/Options.lb deleted file mode 100644 index 7865fa3251..0000000000 --- a/src/mainboard/asi/mb_5blgp/Options.lb +++ /dev/null @@ -1,103 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_VIDEO_MB -uses CONFIG_SPLASH_GRAPHIC -uses CONFIG_GX1_VIDEO -uses CONFIG_GX1_VIDEOMODE -uses CONFIG_PIRQ_ROUTE - -## Enable VGA with a splash screen (only 640x480 to run on most monitors). -## We want to support up to 1024x768@16 so we need 2MiB video memory. -## Note: Higher resolutions might need faster SDRAM speed. -default CONFIG_GX1_VIDEO = 1 -default CONFIG_GX1_VIDEOMODE = 0 -default CONFIG_SPLASH_GRAPHIC = 1 -default CONFIG_VIDEO_MB = 2 - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 3 # Override this in targets/*/Config.lb. -default CONFIG_PIRQ_ROUTE = 1 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc " -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 - -end diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb deleted file mode 100644 index 93ac8e6fb6..0000000000 --- a/src/mainboard/asi/mb_5blmp/Config.lb +++ /dev/null @@ -1,146 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - -## -## Romcc output -## -# makerule ./failover.E -# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" -# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -# end -# -# makerule ./failover.inc -# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" -# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -# end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -# if CONFIG_USE_FALLBACK_IMAGE -# ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -# end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 off end # Ethernet (Realtek RTL8139B) - device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.4 on # PS/2 keyboard (+ mouse?) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - # irq 0x72 = 12 - end - device pnp 2e.a on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.f off # Floppy - io 0x60 = 0x3f2 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.10 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.12 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end - chip cpu/amd/model_gx1 # CPU - end -end - diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb deleted file mode 100644 index 8924226889..0000000000 --- a/src/mainboard/asi/mb_5blmp/Options.lb +++ /dev/null @@ -1,163 +0,0 @@ -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -# uses CONFIG_CONSOLE_VGA -# uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256 * 1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=5 -default CONFIG_PIRQ_ROUTE=1 -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to export a CMOS option table -## -# default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -# default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -# VGA Console -# default CONFIG_CONSOLE_VGA=1 -# default CONFIG_PCI_ROM_RUN=1 -default CONFIG_VIDEO_MB = 0 - -end diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb deleted file mode 100644 index 374629c5b3..0000000000 --- a/src/mainboard/asus/a8n_e/Config.lb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end -driver mainboard.o -# Needed by irq_tables and mptable and acpi_tables. -object get_bus_conf.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/amd/car/cache_as_ram.lds - end -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end -# Include an ID string (for safe flashing). -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -# ROMSTRAP table for CK804. -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -end - mainboardinit cpu/amd/car/cache_as_ram.inc -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # Socket 939 CPU - device apic 0 on end # APIC - end - end - - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 0x00 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x71 = 2 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - irq 0x71 = 2 - end - device pnp 2e.7 on # GPIO config - io 0x60 = 0x0800 - # Set GPIO 1 & 2 - io 0x25 = 0x0000 - # Set GPIO 3 & 4 - io 0x27 = 0x2540 - # GPIO Polarity for Set 3 - io 0xb2 = 0x2100 - # GPIO Pin Internal Pull up for Set 3 - io 0xba = 0x0100 - # Simple I/O register config - io 0xc0 = 0x0000 - io 0xc2 = 0x2540 - io 0xc8 = 0x0000 - io 0xca = 0x0500 - end - device pnp 2e.8 on # Midi port - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a off # IR (N/A on this board) - io 0x60 = 0x310 - irq 0x70 = 11 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic #dimm 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic #dimm 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic #dimm 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic #dimm 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic #dimm 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic #dimm 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic #dimm 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic #dimm 1-1-1 - # device i2c 57 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb deleted file mode 100644 index a03db4bb0b..0000000000 --- a/src/mainboard/asus/a8n_e/Options.lb +++ /dev/null @@ -1,168 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_AP_CODE_IN_CAR -uses CONFIG_MEM_TRAIN_SEQ -uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_ID_SECTION_OFFSET - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 13 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_OPTION_TABLE = 1 -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -# SMP support (only worry about 2 micro processors). -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -# 1G memory hole. -default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0 -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10 -# Make the SB HT chain on bus 0, default is not (0). -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 -# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console -default CONFIG_CONSOLE_VGA = 1 # For VGA console -default CONFIG_PCI_ROM_RUN = 1 # For VGA console -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 -default CONFIG_USE_INIT = 0 -default CONFIG_AP_CODE_IN_CAR = 0 -default CONFIG_MEM_TRAIN_SEQ = 2 -default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 -# default CONFIG_ENABLE_APIC_EXT_ID = 0 -# default CONFIG_APIC_ID_OFFSET = 0x10 -# default CONFIG_LIFT_BSP_APIC_ID = 0 -# default CONFIG_PCI_64BIT_PREF_MEM = 1 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E" -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -# Only use the option table in a normal image. -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR=1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -default CONFIG_ID_SECTION_OFFSET = 0x80 - -end diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb deleted file mode 100644 index 308a1fecef..0000000000 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ /dev/null @@ -1,190 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - -driver mainboard.o -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - mainboardinit southbridge/via/k8t890/romstrap.inc - ldscript /southbridge/via/k8t890/romstrap.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - mainboardinit cpu/amd/car/cache_as_ram.inc - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard (off) - end - device pnp 2e.106 off # Serial flash - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO_PLED - end - device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb deleted file mode 100644 index 92c51feb0c..0000000000 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ /dev/null @@ -1,165 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License v2 as published by -## the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -# uses CONFIG_USE_OPTION_TABLE -# uses CONFIG_RAMTOP -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -# bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -# bx_b005+ -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_USE_PRINTK_IN_CAR - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -default CONFIG_GENERATE_ACPI_TABLES = 1 - -# 1G memory hole -# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 - -# Opteron K8 1G HT support -default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 - -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 - -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 - -# Make the SB HT chain on bus 0, default is not (0). -# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 - -# bx_b005+ make the SB HT chain on bus 0. -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 - -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 - -default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. -default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xcc000 -default CONFIG_DCACHE_RAM_SIZE = 0x4000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 -default CONFIG_USE_INIT = 0 -default CONFIG_ENABLE_APIC_EXT_ID = 0 -default CONFIG_APIC_ID_OFFSET = 0x10 -default CONFIG_LIFT_BSP_APIC_ID = 0 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 256 * 1024 -# More 1M for pgtbl. -# default CONFIG_RAMTOP = 2048*1024 -default CONFIG_RAMBASE = 0x00004000 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR = 1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -end diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb deleted file mode 100644 index 908d1b7309..0000000000 --- a/src/mainboard/asus/m2v-mx_se/Config.lb +++ /dev/null @@ -1,167 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -driver mainboard.o -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - mainboardinit southbridge/via/k8t890/romstrap.inc - ldscript /southbridge/via/k8t890/romstrap.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - mainboardinit cpu/amd/car/cache_as_ram.inc - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x1d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR - end - end - device pci 12.0 on end # VIA LAN - device pci 13.0 on end # br - device pci 13.1 on end # br2 need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8M890 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb deleted file mode 100644 index eaa7168682..0000000000 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ /dev/null @@ -1,174 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License v2 as published by -## the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_RAMTOP -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_MAINBOARD_RESOURCES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_LOW_TABLES -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_VGA -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -# bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -# bx_b005+ -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_USE_PRINTK_IN_CAR - -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_OPTION_TABLE = 1 # FIXME -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -default CONFIG_GENERATE_ACPI_TABLES = 1 -default CONFIG_HAVE_MAINBOARD_RESOURCES = 1 -default CONFIG_HAVE_LOW_TABLES = 0 -default CONFIG_HAVE_ACPI_RESUME = 1 - -# 1G memory hole -# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 - -# Opteron K8 1G HT support -default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 - -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 - -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 - -# Make the SB HT chain on bus 0, default is not (0). -# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 - -# bx_b005+ make the SB HT chain on bus 0. -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 - -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 - -default CONFIG_VGA = 1 -default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. -default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xcc000 -default CONFIG_DCACHE_RAM_SIZE = 0x4000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 -default CONFIG_USE_INIT = 0 -default CONFIG_ENABLE_APIC_EXT_ID = 0 -default CONFIG_APIC_ID_OFFSET = 0x10 -default CONFIG_LIFT_BSP_APIC_ID = 0 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 256 * 1024 -# More 1M for pgtbl. -default CONFIG_RAMTOP = 32768*1024 -# to 1MB -default CONFIG_RAMBASE = 0x1F00000 -default CONFIG_USE_OPTION_TABLE = 0 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR=1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" - -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -end diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb deleted file mode 100644 index af6423c01b..0000000000 --- a/src/mainboard/asus/mew-am/Config.lb +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -# TODO: On-board graphics. -chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 2e.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb deleted file mode 100644 index c62bf48e49..0000000000 --- a/src/mainboard/asus/mew-am/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. -default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. - -end diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb deleted file mode 100644 index 3cd4db2e5f..0000000000 --- a/src/mainboard/asus/mew-vm/Config.lb +++ /dev/null @@ -1,147 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i82810 - device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on # Onboard Video - # device pci 1.0 on end - end - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI Bridge - # device pci 1.0 on end - end - device pci 1f.0 on # ISA/LPC? Bridge - chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.a off end # ACPI - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC'97, no header on MEW-VM - device pci 1f.6 off end # AC'97 Modem (MC'97) - end - end - chip cpu/intel/socket_PGA370 - end -end - diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb deleted file mode 100644 index 50f0b54a7a..0000000000 --- a/src/mainboard/asus/mew-vm/Options.lb +++ /dev/null @@ -1,154 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 512*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT = 1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE = 0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET = 0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 11 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE = 0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -default CONFIG_UDELAY_TSC=1 - -end diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb deleted file mode 100644 index 1170d4c091..0000000000 --- a/src/mainboard/asus/p2b-d/Config.lb +++ /dev/null @@ -1,134 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 1 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb deleted file mode 100644 index 2ccd3a9d26..0000000000 --- a/src/mainboard/asus/p2b-d/Options.lb +++ /dev/null @@ -1,103 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_SMP -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_IOAPIC = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -end diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb deleted file mode 100644 index 4307c39442..0000000000 --- a/src/mainboard/asus/p2b-ds/Config.lb +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 1 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb deleted file mode 100644 index 45214cf0a3..0000000000 --- a/src/mainboard/asus/p2b-ds/Options.lb +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_SMP -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_IOAPIC = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb deleted file mode 100644 index 4be4b44b6b..0000000000 --- a/src/mainboard/asus/p2b-f/Config.lb +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb deleted file mode 100644 index 68843932f1..0000000000 --- a/src/mainboard/asus/p2b-f/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb deleted file mode 100644 index 559694de3c..0000000000 --- a/src/mainboard/asus/p2b/Config.lb +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb deleted file mode 100644 index 0d1bb91ca8..0000000000 --- a/src/mainboard/asus/p2b/Options.lb +++ /dev/null @@ -1,98 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb deleted file mode 100644 index 628c41372b..0000000000 --- a/src/mainboard/asus/p3b-f/Config.lb +++ /dev/null @@ -1,133 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -# TODO -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb deleted file mode 100644 index 1320c2612d..0000000000 --- a/src/mainboard/asus/p3b-f/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb deleted file mode 100644 index e802587bb3..0000000000 --- a/src/mainboard/axus/tc320/Config.lb +++ /dev/null @@ -1,126 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe800 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 off end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - # register "ide0_enable" = "1" - # register "ide1_enable" = "1" - end - end - chip cpu/amd/model_gx1 # CPU - end -end diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb deleted file mode 100644 index b0fd16ebca..0000000000 --- a/src/mainboard/axus/tc320/Options.lb +++ /dev/null @@ -1,103 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_VIDEO_MB -uses CONFIG_SPLASH_GRAPHIC -uses CONFIG_GX1_VIDEO -uses CONFIG_GX1_VIDEOMODE -uses CONFIG_PIRQ_ROUTE - -## Enable VGA with a splash screen (only 640x480 to run on most monitors). -## We want to support up to 1024x768@16 so we need 2MiB video memory. -## Note: Higher resolutions might need faster SDRAM speed. -default CONFIG_GX1_VIDEO = 1 -default CONFIG_GX1_VIDEOMODE = 0 -default CONFIG_SPLASH_GRAPHIC = 1 -default CONFIG_VIDEO_MB = 2 - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_MAINBOARD_VENDOR = "AXUS" -default CONFIG_MAINBOARD_PART_NUMBER = "TC320" -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots -default CONFIG_PIRQ_ROUTE = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc " -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 - -end diff --git a/src/mainboard/azza/pt-6ibd/Config.lb b/src/mainboard/azza/pt-6ibd/Config.lb deleted file mode 100644 index b4f2224fc2..0000000000 --- a/src/mainboard/azza/pt-6ibd/Config.lb +++ /dev/null @@ -1,131 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/azza/pt-6ibd/Options.lb b/src/mainboard/azza/pt-6ibd/Options.lb deleted file mode 100644 index 68843932f1..0000000000 --- a/src/mainboard/azza/pt-6ibd/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/bcom/winnet100/Config.lb b/src/mainboard/bcom/winnet100/Config.lb deleted file mode 100644 index ccd4fb128b..0000000000 --- a/src/mainboard/bcom/winnet100/Config.lb +++ /dev/null @@ -1,129 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 on end # Ethernet (onboard) - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, Advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 (used for smartcard reader) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe8 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - register "ide0_enable" = "1" - register "ide1_enable" = "0" # Not available/needed on this board - end - end - chip cpu/amd/model_gx1 # CPU - end -end diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb deleted file mode 100644 index d241356d54..0000000000 --- a/src/mainboard/bcom/winnet100/Options.lb +++ /dev/null @@ -1,103 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_VIDEO_MB -uses CONFIG_SPLASH_GRAPHIC -uses CONFIG_GX1_VIDEO -uses CONFIG_GX1_VIDEOMODE -uses CONFIG_PIRQ_ROUTE - -## Enable VGA with a splash screen (only 640x480 to run on most monitors). -## We want to support up to 1024x768@16 so we need 2MiB video memory. -## Note: Higher resolutions might need faster SDRAM speed. -default CONFIG_GX1_VIDEO = 1 -default CONFIG_GX1_VIDEOMODE = 0 -default CONFIG_SPLASH_GRAPHIC = 1 -default CONFIG_VIDEO_MB = 2 - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_MAINBOARD_VENDOR = "BCOM" -default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100" -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots -default CONFIG_PIRQ_ROUTE = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc " -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 - -end diff --git a/src/mainboard/bcom/winnetp680/Config.lb b/src/mainboard/bcom/winnetp680/Config.lb deleted file mode 100644 index ed036503d6..0000000000 --- a/src/mainboard/bcom/winnetp680/Config.lb +++ /dev/null @@ -1,138 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci f.0 on end # IDE - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, GPIO 1 - device pnp 2e.8 off end # MIDI port, GPIO 5 - device pnp 2e.9 off end # GPIO 2-4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM - io 0x60 = 0x290 - end - end - end - device pci 11.5 on end # AC'97 audio - device pci 12.0 on end # Ethernet - end - end - device apic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC - end - end -end diff --git a/src/mainboard/bcom/winnetp680/Options.lb b/src/mainboard/bcom/winnetp680/Options.lb deleted file mode 100644 index 99bd7f49ae..0000000000 --- a/src/mainboard/bcom/winnetp680/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_VIDEO_MB -uses CONFIG_SMP -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_SMP = 1 -default CONFIG_IOAPIC = 1 -default CONFIG_VIDEO_MB = 32 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 10 -default CONFIG_GENERATE_ACPI_TABLES = 0 -default CONFIG_HAVE_OPTION_TABLE = 1 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_USE_FALLBACK_IMAGE = 1 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" - -end diff --git a/src/mainboard/biostar/m6tba/Config.lb b/src/mainboard/biostar/m6tba/Config.lb deleted file mode 100644 index 20edbc9b4c..0000000000 --- a/src/mainboard/biostar/m6tba/Config.lb +++ /dev/null @@ -1,126 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.8 on # Aux I/O - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/biostar/m6tba/Options.lb b/src/mainboard/biostar/m6tba/Options.lb deleted file mode 100644 index 68843932f1..0000000000 --- a/src/mainboard/biostar/m6tba/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb deleted file mode 100644 index 238596d256..0000000000 --- a/src/mainboard/broadcom/blast/Config.lb +++ /dev/null @@ -1,235 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for broadcom/blast -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on # Legacy pci main 0x0205 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 71 on end #0 pca9554 0 - device i2c 71 on end #0 pca9554 1 - device i2c 71 on end #0 pca9554 2 - device i2c 71 on end #0 pca9554 3 - device i2c 71 on end #0 pca9554 4 - device i2c 71 on end #0 pca9554 5 - device i2c 71 on #0 pca9554 6 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 71 on #1 pca9554 7 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - end - end - - end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end - end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 4.0 on end # it is in bcm5785_0 bus - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - - - end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - -end - diff --git a/src/mainboard/broadcom/blast/Options.lb b/src/mainboard/broadcom/blast/Options.lb deleted file mode 100644 index 208a6c7433..0000000000 --- a/src/mainboard/broadcom/blast/Options.lb +++ /dev/null @@ -1,260 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -#default CONFIG_CONSOLE_VGA=1 -#default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset -default CONFIG_HT_CHAIN_UNITID_BASE=0x6 - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="blast" -default CONFIG_MAINBOARD_VENDOR="Broadcom" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb deleted file mode 100644 index 49f1585d6b..0000000000 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb +++ /dev/null @@ -1,136 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - device pci a.0 on end # NIC (onboard) - chip southbridge/intel/i82371eb # Southbridge - device pci 14.0 on # ISA bridge - # chip superio/nsc/pc97307 # Super I/O - chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!) - device pnp 15c.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 15c.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 15c.2 on # RTC, APC - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 15c.3 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 15c.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 15c.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 15c.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 15c.7 on # GPIO 1 - end - device pnp 15c.8 on # Power management - end - end - end - device pci 14.1 on end # IDE - device pci 14.2 on end # USB - device pci 14.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb deleted file mode 100644 index dd8ab0256b..0000000000 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 5 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb deleted file mode 100644 index cc0edc6a8b..0000000000 --- a/src/mainboard/dell/s1850/Config.lb +++ /dev/null @@ -1,174 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8e8b8f80" - register "pirq_e_h" = "0x80808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb deleted file mode 100644 index fb65f8d8e2..0000000000 --- a/src/mainboard/dell/s1850/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -#default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb deleted file mode 100644 index c20323109f..0000000000 --- a/src/mainboard/digitallogic/adl855pc/Config.lb +++ /dev/null @@ -1,159 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -## This does not look right but it is a literal conversion of the -## old version of this file. -chip northbridge/intel/i855pm - device pci_domain 0 on - device pci 0.0 on end - device pci 1.0 on end - chip southbridge/intel/i82801dbm -# pci 11.0 on end -# pci 11.1 on end -# pci 11.2 on end -# pci 11.3 on end -# pci 11.4 on end -# pci 11.5 on end -# pci 11.6 on end -# pci 12.0 on end - register "enable_usb" = "0" - register "enable_native_ide" = "0" - register "enable_usb" = "0" - register "enable_native_ide" = "0" - chip superio/winbond/w83627hf # link 1 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" - end - end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA479M - device apic 0 on end - end - end -end diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb deleted file mode 100644 index 5c7ee6e6db..0000000000 --- a/src/mainboard/digitallogic/adl855pc/Options.lb +++ /dev/null @@ -1,107 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_UDELAY_IO -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY - -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 1024*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## use io based udelay function -## -default CONFIG_UDELAY_IO=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=5 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -end diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb deleted file mode 100644 index dbd3e64447..0000000000 --- a/src/mainboard/digitallogic/msm586seg/Config.lb +++ /dev/null @@ -1,111 +0,0 @@ -default CONFIG_ROM_SIZE = 512 * 1024 - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 32 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - - -# VGA console -if CONFIG_CONSOLE_VGA - default CONFIG_PCI_ROM_RUN=1 -end -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -dir /devices -config chip.h - -chip cpu/amd/sc520 - device pci_domain 0 on - device pci 0.0 on end - device pci 12.0 on end # enet - device pci 14.0 on end # 69000 -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" - end - -end diff --git a/src/mainboard/digitallogic/msm586seg/Options.lb b/src/mainboard/digitallogic/msm586seg/Options.lb deleted file mode 100644 index 1bd5cae41a..0000000000 --- a/src/mainboard/digitallogic/msm586seg/Options.lb +++ /dev/null @@ -1,121 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_COMPRESS -uses CONFIG_ROM_PAYLOAD -uses CONFIG_USE_INIT -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY - -uses CONFIG_CONSOLE_SERIAL8250 - - -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL - -# VGA support -uses CONFIG_CONSOLE_VGA -#uses CONFIG_LEGACY_VGABIOS -#uses VGABIOS_START -uses CONFIG_PCI_ROM_RUN - - -default CONFIG_CONSOLE_SERIAL8250=1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -end diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb deleted file mode 100644 index 5965cc1d0a..0000000000 --- a/src/mainboard/digitallogic/msm800sev/Config.lb +++ /dev/null @@ -1,170 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - # How to get these? Boot linux and do this: - # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x0000105a" - # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EFA5" - # mode is high 10 bits (determined from code) - register "lpc_serirq_mode" = "1" - # Don't yet know how to find this. - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3F8" - register "com1_irq" = "4" - register "com2_enable" = "0" - register "com2_address" = "0x2F8" - register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci f.1 on end # Flash controller - device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end - -end - diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb deleted file mode 100644 index 88e2a1f0e2..0000000000 --- a/src/mainboard/digitallogic/msm800sev/Options.lb +++ /dev/null @@ -1,180 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_VIDEO_MB=8 -default CONFIG_PCI_ROM_RUN=0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 -default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 32768 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb deleted file mode 100644 index 64e833f938..0000000000 --- a/src/mainboard/eaglelion/5bcm/Config.lb +++ /dev/null @@ -1,150 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 - device pci_domain 0 on - device pci 0.0 on end - chip southbridge/amd/cs5530 - device pci 12.0 on - chip superio/nsc/pc97317 - device pnp 2e.0 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # FDC - end - device pnp 2e.4 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power Management - io 0x60 = 0xe800 - end - register "com1" = "{115200}" - register "com2" = "{38400}" - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA - end - end - end - - chip cpu/amd/model_gx1 - end - -end - diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb deleted file mode 100644 index fb2bfae81e..0000000000 --- a/src/mainboard/eaglelion/5bcm/Options.lb +++ /dev/null @@ -1,164 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_VIDEO_MB -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -default CONFIG_VIDEO_MB = 0 - -end diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb deleted file mode 100644 index 7357648411..0000000000 --- a/src/mainboard/emulation/qemu-x86/Config.lb +++ /dev/null @@ -1,131 +0,0 @@ -## we don't use CONFIG_USE_DCACHE_RAM by default -default CONFIG_USE_DCACHE_RAM=0 -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE - -## -## Compute where this copy of coreboot will start in the boot rom -## -default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## CONFIG_XIP_ROM_SIZE must be a power of 2. -## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE -## -default CONFIG_XIP_ROM_SIZE=32*1024 -default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - -## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. -## That way, later, we can simply yank them if we wish. -## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. -## we do not use failover yet in this case. This is a work in progress. -if CONFIG_USE_DCACHE_RAM - ## - ## - mainboardinit arch/i386/init/entry.S - mainboardinit arch/i386/init/car.S - ldscript /arch/i386/init/ldscript.ld - - ## The main code for the rom section is called rom.c - initobject rom.o -else - ## - ## Romcc output - ## - makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" - end - - makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" - end - - makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" - end - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" - end - - ## - ## Build our 16 bit and 32 bit coreboot entry code - ## - mainboardinit cpu/x86/16bit/entry16.inc - mainboardinit cpu/x86/32bit/entry32.inc - ldscript /cpu/x86/16bit/entry16.lds - ldscript /cpu/x86/32bit/entry32.lds - - ## - ## Build our reset vector (This is where coreboot is entered) - ## - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - - ### Should this be in the northbridge code? - mainboardinit arch/i386/lib/cpu_reset.inc - - ## - ## Setup RAM - ## - mainboardinit cpu/x86/fpu_enable.inc - mainboardinit ./auto.inc - - ## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future. - ## - ## Include an id string (For safe flashing) - ## - mainboardinit arch/i386/lib/id.inc - ldscript /arch/i386/lib/id.lds - -## -## end of CONFIG_USE_DCACHE_RAM bits. -## -end - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip cpu/emulation/qemu-x86 - device pci_domain 0 on - device pci 0.0 on end - - chip southbridge/intel/i82371eb # southbridge - device pci 01.0 on end - device pci 01.1 on end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" - end -end diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb deleted file mode 100644 index e0671284a8..0000000000 --- a/src/mainboard/emulation/qemu-x86/Options.lb +++ /dev/null @@ -1,140 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_WRITE_HIGH_TABLES -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_PCI_ROM_RUN -uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE - -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL - -uses CONFIG_UDELAY_IO -default CONFIG_UDELAY_IO=1 - -default CONFIG_CONSOLE_SERIAL8250=1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=6 - -default CONFIG_WRITE_HIGH_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Option ROM init -## -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## known-good settings for qemu -default CONFIG_DCACHE_RAM_BASE=0x8f000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 - - - - -end diff --git a/src/mainboard/gigabyte/ga-6bxc/Config.lb b/src/mainboard/gigabyte/ga-6bxc/Config.lb deleted file mode 100644 index 663f58e153..0000000000 --- a/src/mainboard/gigabyte/ga-6bxc/Config.lb +++ /dev/null @@ -1,130 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.2 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.4 on # APC - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 3f0.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 3f0.7 on # GPIO - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/gigabyte/ga-6bxc/Options.lb b/src/mainboard/gigabyte/ga-6bxc/Options.lb deleted file mode 100644 index 8189979485..0000000000 --- a/src/mainboard/gigabyte/ga-6bxc/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb deleted file mode 100644 index 6cca586272..0000000000 --- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ /dev/null @@ -1,270 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) -## Written by Morgan Tsai <my_tsai@sis.com> for SiS. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/sis/sis966/romstrap.inc - ldscript /southbridge/sis/sis966/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/sis/sis966/romstrap.inc - ldscript /southbridge/sis/sis966/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_AM2 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/sis/sis966 - device pci 0.0 on end # Northbridge - device pci 1.0 on # AGP bridge - device pci 0.0 on end - end - device pci 2.0 on # LPC - chip superio/ite/it8716f - device pnp 2e.0 off # Floppy (N/A) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel port (N/A) - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 off # PS/2 keyboard (N/A) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse (N/A) - irq 0x70 = 12 - end - device pnp 2e.8 off # MIDI (N/A) - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME (N/A) - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR (N/A) - end - end - - device pci 2.5 off end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183,Native Mode) - device pci 6.0 on end # PCI-e x1 - device pci 7.0 on end # PCI-e x1 - device pci a.0 off end - device pci b.0 off end - device pci c.0 off end - device pci d.0 off end - device pci e.0 off end - device pci f.0 off end # HD Audio (SiS7502) - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb deleted file mode 100644 index 6cbef12918..0000000000 --- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ /dev/null @@ -1,354 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) -## Written by Morgan Tsai <my_tsai@sis.com> for SiS. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 -#default CONFIG_ROM_SIZE=0x100000 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=0 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#default CONFIG_USBDEBUG_DIRECT=0 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk" -default CONFIG_MAINBOARD_VENDOR="GIGABYTE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 -### End Options.lb -end diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb deleted file mode 100644 index c84d73c724..0000000000 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ /dev/null @@ -1,362 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL - object fanctl.o -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## ACPI Support -## -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv $(CURDIR)/dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_AM2 - device apic 0 on end - end -end -device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f - # Floppy and any LDN - device pnp 2e.0 on - # Watchdog from CLKIN, CLKIN = 24 MHz - irq 0x23 = 0x11 - # Serial Flash (SPI only) - #0x24 = 0x1a - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO, SPI flash - # pin 84 is not GP10 - irq 0x25 = 0x0 - # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 - irq 0x26 = 0x43 - # pin 13 is GP35 - irq 0x27 = 0x20 - # pin 70 is not GP46 - #irq 0x28 = 0x0 - # pin 6,3,128,127,126 is GP63,64,65,66,67 - irq 0x29 = 0x81 - # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V - #irq 0x2c = 0x1f - # Simple I/O base - io 0x62 = 0x800 - # Serial Flash I/O (SPI only) - io 0x64 = 0x820 - # watch dog force timeout (parallel flash only) - #irq 0x71 = 0x1 - # No WDT interrupt - irq 0x72 = 0x0 - # GPIO pin set 1 disable internal pullup - irq 0xb8 = 0x0 - # GPIO pin set 5 enable internal pullup - irq 0xbc = 0x01 - # SIO pin set 1 alternate function - #irq 0xc0 = 0x0 - # SIO pin set 2 mixed function - irq 0xc1 = 0x43 - # SIO pin set 3 mixed function - irq 0xc2 = 0x20 - # SIO pin set 4 alternate function - #irq 0xc3 = 0x0 - # SIO pin set 1 input mode - #irq 0xc8 = 0x0 - # SIO pin set 2 input mode - irq 0xc9 = 0x0 - # SIO pin set 4 input mode - #irq 0xcb = 0x0 - # Generate SMI# on EC IRQ - #irq 0xf0 = 0x10 - # SMI# level trigger - #irq 0xf1 = 0x40 - # HWMON alert beep pin location - irq 0xf6 = 0x28 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM -#WTF?!? We already have device pci 1.1 in the section above - device pci 1.1 on # SM 1 - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end #device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb deleted file mode 100644 index 3010a2ad68..0000000000 --- a/src/mainboard/gigabyte/m57sli/Options.lb +++ /dev/null @@ -1,364 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_WRITE_HIGH_TABLES - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL - -uses CONFIG_ID_SECTION_OFFSET -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 -#default CONFIG_ROM_SIZE=0x100000 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Set-up automatic fan control -## -default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## HIGH tables support -default CONFIG_WRITE_HIGH_TABLES=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#default CONFIG_USBDEBUG_DIRECT=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="m57sli" -default CONFIG_MAINBOARD_VENDOR="GIGABYTE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/hp/dl145_g3/Config.lb b/src/mainboard/hp/dl145_g3/Config.lb deleted file mode 100644 index 6c0508e217..0000000000 --- a/src/mainboard/hp/dl145_g3/Config.lb +++ /dev/null @@ -1,210 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 AMD -## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. -## -## Copyright (C) 2007 University of Mannheim -## Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim -## -## Copyright (C) 2009 University of Heidelberg -## Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end -else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - - -# config for hp/dl145_g3 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 # northbridge - device pci 18.0 on # devices on link 0 - chip southbridge/broadcom/bcm21000 # HT2100 - device pci 0.0 on - end # bridge to slot PCI-E 4x ?? - device pci 1.0 on - end - device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? - end - device pci 4.0 on - end # unused - device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC - end - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.3 off # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA - end - end - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # amdk8 - - end #pci_domain -end - - diff --git a/src/mainboard/hp/dl145_g3/Options.lb b/src/mainboard/hp/dl145_g3/Options.lb deleted file mode 100644 index 5ae7fb27c5..0000000000 --- a/src/mainboard/hp/dl145_g3/Options.lb +++ /dev/null @@ -1,328 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 AMD -## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. -## -## Copyright (C) 2007 University of Mannheim -## Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for Uni Mannheim -## Copyright (C) 2009 University of Heidelberg -## Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x8 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=0 - -#HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x06 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcc000 -default CONFIG_DCACHE_RAM_SIZE=0x04000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="DL145 G3" -default CONFIG_MAINBOARD_VENDOR="HP" -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -#enabel printk in CAR by default -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/hp/e_vectra_p2706t/Config.lb b/src/mainboard/hp/e_vectra_p2706t/Config.lb deleted file mode 100644 index c158b8178b..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/Config.lb +++ /dev/null @@ -1,128 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -# TODO: i810E actually! -chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - # TODO: PC87364 actually! - # TODO: Check Super I/O settings and compare to superiotool -d. - chip superio/nsc/pc87360 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # PS/2 mouse - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A ?) - end - end -end - diff --git a/src/mainboard/hp/e_vectra_p2706t/Options.lb b/src/mainboard/hp/e_vectra_p2706t/Options.lb deleted file mode 100644 index ff43b4f129..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/Options.lb +++ /dev/null @@ -1,101 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VGA_ROM_RUN -uses CONFIG_WRITE_HIGH_TABLES -uses CONFIG_VIDEO_MB - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 3 -default CONFIG_MAINBOARD_VENDOR = "HP" -default CONFIG_MAINBOARD_PART_NUMBER = "e-Vectra P2706T" -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_VGA_ROM_RUN = 1 -default CONFIG_WRITE_HIGH_TABLES = 1 -default CONFIG_VIDEO_MB = 1 -end diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb deleted file mode 100644 index ad37abadd2..0000000000 --- a/src/mainboard/ibm/e325/Config.lb +++ /dev/null @@ -1,185 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - - -chip northbridge/amd/amdk8/root_complex - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 - chip southbridge/amd/amd8131 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - end - end # device pci 18.0 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end -end - diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb deleted file mode 100644 index a745e187d1..0000000000 --- a/src/mainboard/ibm/e325/Options.lb +++ /dev/null @@ -1,221 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=12 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=1 -default CONFIG_MAX_PHYSICAL_CPUS=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="E325" -default CONFIG_MAINBOARD_VENDOR="IBM" -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb deleted file mode 100644 index 08109ee165..0000000000 --- a/src/mainboard/ibm/e326/Config.lb +++ /dev/null @@ -1,178 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 - chip southbridge/amd/amd8131 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 off end - device pci 5.0 on end # ATI Rage XL - end - device pci 1.0 on - chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end - diff --git a/src/mainboard/ibm/e326/Options.lb b/src/mainboard/ibm/e326/Options.lb deleted file mode 100644 index 265ae756da..0000000000 --- a/src/mainboard/ibm/e326/Options.lb +++ /dev/null @@ -1,227 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=12 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=2 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -#VGA -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="E326" -default CONFIG_MAINBOARD_VENDOR="IBM" -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb deleted file mode 100644 index c87ea5c70e..0000000000 --- a/src/mainboard/iei/juki-511p/Config.lb +++ /dev/null @@ -1,157 +0,0 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -default CONFIG_ROM_SIZE = 256 * 1024 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## CONFIG_XIP_ROM_SIZE must be a power of 2. -## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE -## -default CONFIG_XIP_ROM_SIZE=65536 -default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -mainboardinit cpu/x86/16bit/reset16.inc -ldscript /cpu/x86/16bit/reset16.lds - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -#dir /pc80 -#config chip.h - -chip northbridge/amd/gx1 - device pci_domain 0 on - device pci 0.0 on end - chip southbridge/amd/cs5530 - - device pci 12.0 on - chip superio/winbond/w83977f - device pnp 3f0.0 on # FDC - irq 0x70 = 6 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - register "com1" = "{115200}" - device pnp 3f0.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - register "com2" = "{115200}" - device pnp 3f0.4 on # RTC - io 0x60 = 0x070 - irq 0x70 = 8 - end - device pnp 3f0.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Int 1 for PS/2 keyboard - irq 0x72 = 12 # Int 12 for PS/2 mouse - end - device pnp 3f0.6 off # IR - end - device pnp 3f0.7 off # GPIO1 - end - device pnp 3f0.8 off # GPIO - end - end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA onboard - - end - - device pci 0e.0 on end # ETH0 - device pci 13.0 on end # USB - - end - end - - chip cpu/amd/model_gx1 - end - -end - diff --git a/src/mainboard/iei/juki-511p/Options.lb b/src/mainboard/iei/juki-511p/Options.lb deleted file mode 100644 index d7fde57fd0..0000000000 --- a/src/mainboard/iei/juki-511p/Options.lb +++ /dev/null @@ -1,145 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_UDELAY_IO -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_VIDEO_MB -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -default CONFIG_UDELAY_IO=1 -## -## Build code to export a programmable irq routing table -## -# FIXME: There's an irq_tables.c file, but CONFIG_GENERATE_PIRQ_TABLE is 0. -default CONFIG_GENERATE_PIRQ_TABLE=0 -default CONFIG_IRQ_SLOT_COUNT=2 -default CONFIG_PIRQ_ROUTE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -default CONFIG_VIDEO_MB = 0 - -end diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb deleted file mode 100644 index 3fd6ce70dd..0000000000 --- a/src/mainboard/iei/nova4899r/Config.lb +++ /dev/null @@ -1,163 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -#dir /pc80 -#config chip.h - -chip northbridge/amd/gx1 - device pci_domain 0 on - device pci 0.0 on end - chip southbridge/amd/cs5530 - device pci 0a.0 on end # ETH0 - device pci 0b.0 off end # ETH1 - device pci 0c.0 on end # ETH2 - device pci 0f.0 on end # PCI slot - device pci 12.0 on - chip superio/winbond/w83977tf - device pnp 2e.0 on # FDC - irq 0x70 = 6 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - register "com1" = "{115200}" - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - register "com2" = "{115200}" - device pnp 2e.4 off # Reserved - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 0x01 # Int 1 for PS/2 keyboard - irq 0x72 = 0x0c # Int 12 for PS/2 mouse - end - device pnp 2e.6 on # IR - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.7 on # GAME/MIDI/GPIO1 - io 0x60 = 0x290 - end - device pnp 2e.8 on # GPIO2 - io 0x60 = 0x110 - end - device pnp 2e.9 on # GPIO3 - io 0x60 = 0x120 - end - device pnp 2e.A on # Power Management - io 0x60 = 0xe800 - end - end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA onboard - end - device pci 13.0 on end # USB - end - end - - chip cpu/amd/model_gx1 - end - -end - diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb deleted file mode 100644 index 564a441836..0000000000 --- a/src/mainboard/iei/nova4899r/Options.lb +++ /dev/null @@ -1,172 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_VIDEO_MB -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=0 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=5 -default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 - -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -default CONFIG_VIDEO_MB = 0 - -end diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb deleted file mode 100644 index 39fc0df5ac..0000000000 --- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb +++ /dev/null @@ -1,136 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - # Compile cache_as_ram.c to auto.inc. - makerule ./cache_as_ram_auto.inc - # depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc -dir /pc80 -config chip.h - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x0000105a" - register "lpc_serirq_polarity" = "0x0000EFA5" - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "1" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3F8" - register "com1_irq" = "4" - register "com2_enable" = "0" - register "com2_address" = "0x2F8" - register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 9.0 on end # Slot1 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot3 - device pci c.0 on end # Slot4 - device pci e.0 on end # Ethernet 0 - device pci 10.0 on end # Ethernet 1 - device pci 11.0 on end # SATA - device pci f.0 on # ISA Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HW Monitor - end - end - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end -end - diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb deleted file mode 100644 index 6ff46bfba7..0000000000 --- a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb +++ /dev/null @@ -1,106 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_IO -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_VIDEO_MB = 8 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_IO = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 9 -default CONFIG_PIRQ_ROUTE = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_ROM_IMAGE_SIZE = 32 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 -default CONFIG_USE_PRINTK_IN_CAR=1 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/intel/d945gclf/Config.lb b/src/mainboard/intel/d945gclf/Config.lb deleted file mode 100644 index 6671471132..0000000000 --- a/src/mainboard/intel/d945gclf/Config.lb +++ /dev/null @@ -1,228 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Image size calculation -## - -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -driver rtl8168.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" - action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" - action "mv $(CURDIR)/dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/x86/car/cache_as_ram.lds -end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/intel/model_106cx/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i945 - - device apic_cluster 0 on - chip cpu/intel/socket_441 - device apic 0 on end - end - end - - device pci_domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "1" - register "gpe0_en" = "0x20000601" - - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" - - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy - end - device pnp 2e.3 off # Parport - end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.7 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.8 on # GAME - # all default - end - device pnp 2e.a on # PME - end - device pnp 2e.b on # MPU - end - end - end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec - end - end -end diff --git a/src/mainboard/intel/d945gclf/Options.lb b/src/mainboard/intel/d945gclf/Options.lb deleted file mode 100644 index 9660b9f569..0000000000 --- a/src/mainboard/intel/d945gclf/Options.lb +++ /dev/null @@ -1,329 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# Tables -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_MAINBOARD_RESOURCES -# SMP -uses CONFIG_SMP -uses CONFIG_LOGICAL_CPUS -uses CONFIG_AP_IN_SIPI_WAIT -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -# Image Size -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -# Payload -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -# Build Internals -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_XIP_ROM_BASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses CONFIG_MMCONF_SUPPORT -uses CONFIG_MMCONF_BASE_ADDRESS -uses CONFIG_GFXUMA - -# -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -# Timers -uses CONFIG_UDELAY_LAPIC -# Console -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_DEBUG -# Toolchain -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -# Tweaks -uses CONFIG_GDB_STUB -uses CONFIG_MAX_REBOOT_CNT -uses CONFIG_USE_WATCHDOG_ON_BOOT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL - -### -### Build options -### - -## -## -default CONFIG_MAX_REBOOT_CNT=3 - -## -## Use the watchdog to break out of a lockup condition -## -default CONFIG_USE_WATCHDOG_ON_BOOT=0 - -## -## ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=CONFIG_FALLBACK_SIZE*2 - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## -default CONFIG_UDELAY_LAPIC=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=1 - -## -## Leave a hole for mmapped PCIe config space -## - -default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default CONFIG_MMCONF_SUPPORT=1 -default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 - -## -## UMA -## -default CONFIG_GFXUMA=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=18 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 -default CONFIG_HAVE_ACPI_RESUME=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default CONFIG_coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -# There are some network option roms that don't work with -# coreboot's x86emu. Thus, we only execute the VGA option rom -# for now: -default CONFIG_VGA_ROM_RUN=1 -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_DEBUG=0 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 -default CONFIG_AP_IN_SIPI_WAIT=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_BASE=0xffed8000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Execute In Place settings -## - -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE ) - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="D945GCLF" -default CONFIG_MAINBOARD_VENDOR= "INTEL" - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x464c - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0xb800 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/intel/eagleheights/Config.lb b/src/mainboard/intel/eagleheights/Config.lb deleted file mode 100644 index ea76cad821..0000000000 --- a/src/mainboard/intel/eagleheights/Config.lb +++ /dev/null @@ -1,212 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.dsl" - action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" - action "mv $(CURDIR)/dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -if CONFIG_HAVE_HARD_RESET object reset.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/x86/car/cache_as_ram.lds -end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -## Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -mainboardinit cpu/intel/model_6ex/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i3100 - device pci_domain 0 on - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x8b808a8a" - register "pirq_e_h" = "0x85808080" - - device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 off end # PCIe port B1 - device pci 1c.2 off end # PCIe port B2 - device pci 1c.3 off end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - chip superio/smsc/smscsuperio - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.2 off # Serial Port 4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 2 - end - device pnp 2e.4 off # Serial Port 3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.7 on # PS/2 Keyboard / Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.a off # Runtime registers - io 0x60 = 0x600 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # Performance counters - end - end - device apic_cluster 0 on - chip cpu/intel/bga956 - device apic 0 on end - end - end -end - diff --git a/src/mainboard/intel/eagleheights/Options.lb b/src/mainboard/intel/eagleheights/Options.lb deleted file mode 100644 index 3a2e7b68c6..0000000000 --- a/src/mainboard/intel/eagleheights/Options.lb +++ /dev/null @@ -1,323 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -# Tables -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_MAINBOARD_RESOURCES -# SMP -uses CONFIG_SMP -uses CONFIG_LOGICAL_CPUS -uses CONFIG_AP_IN_SIPI_WAIT -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -# Image Size -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -# Payload -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_PRECOMPRESSED_PAYLOAD -# Build Internals -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_XIP_ROM_BASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses CONFIG_MMCONF_SUPPORT -uses CONFIG_MMCONF_BASE_ADDRESS -# -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -# Timers -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -# Console -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_DEBUG -uses CONFIG_VGA -uses CONFIG_PCI_OPTION_ROM_RUN_YABEL -# Toolchain -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -# Tweaks -uses CONFIG_GDB_STUB -uses CONFIG_MAX_REBOOT_CNT -uses CONFIG_USE_WATCHDOG_ON_BOOT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL - -### -### Build options -### - -## -## -default CONFIG_MAX_REBOOT_CNT=3 - -## -## Use the watchdog to break out of a lockup condition -## -default CONFIG_USE_WATCHDOG_ON_BOOT=0 - -## -## ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=0 - -## -## Leave a hole for mmapped PCIe config space -## -default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default CONFIG_MMCONF_SUPPORT=1 -default CONFIG_MMCONF_BASE_ADDRESS=0xE0000000 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=0 -# There are some network option roms that don't work with -# coreboot's x86emu. Thus, we only execute the VGA option rom -# for now: -default CONFIG_VGA_ROM_RUN=0 -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_DEBUG=0 - -#default CONFIG_VGA=0 -#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 -default CONFIG_AP_IN_SIPI_WAIT=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024) -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="EagleHeights" -default CONFIG_MAINBOARD_VENDOR= "Intel" - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 -default CONFIG_PRECOMPRESSED_PAYLOAD=1 -default CONFIG_COMPRESSED_PAYLOAD_LZMA=1 -#default CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb deleted file mode 100644 index 722ba4027b..0000000000 --- a/src/mainboard/intel/jarrell/Config.lb +++ /dev/null @@ -1,182 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 - device pci_domain 0 on - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - device pci 00.0 on end - device pci 00.1 on end - device pci 00.2 on - chip drivers/generic/generic - device pci 04.0 on end - device pci 04.1 on end - end - end - device pci 00.3 on end - end - end - device pci 06.0 on end - chip southbridge/intel/i82801er # i82801er - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 off end - device pci 1d.7 on end - device pci 1e.0 on - chip drivers/ati/ragexl - device pci 0c.0 on end - end - end - device pci 1f.0 on - chip superio/nsc/pc87427 - device pnp 2e.0 off end - device pnp 2e.2 on -# io 0x60 = 0x2f8 -# irq 0x70 = 3 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on -# io 0x60 = 0x3f8 -# irq 0x70 = 4 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 on - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end - device pnp 2e.9 off end - device pnp 2e.a off end - device pnp 2e.f on end - device pnp 2e.10 off end - device pnp 2e.14 off end - end - end - device pci 1f.1 on end - device pci 1f.2 off end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" - register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW" - register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT" - end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end - end - end -end diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb deleted file mode 100644 index 91927eee0d..0000000000 --- a/src/mainboard/intel/jarrell/Options.lb +++ /dev/null @@ -1,242 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -uses CONFIG_MAX_REBOOT_CNT -uses CONFIG_USE_WATCHDOG_ON_BOOT - - -### -### Build options -### - -## -## Because we do the stutter start we need more attempts -## -default CONFIG_MAX_REBOOT_CNT=8 - -## -## Use the watchdog to break out of a lockup condition -## -default CONFIG_USE_WATCHDOG_ON_BOOT=1 - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=2097152 - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=18 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D" -default CONFIG_MAINBOARD_VENDOR= "Intel" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb deleted file mode 100644 index 026c45d40e..0000000000 --- a/src/mainboard/intel/mtarvon/Config.lb +++ /dev/null @@ -1,160 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 as -## published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i3100 - device pci_domain 0 on - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 on end # PCIe port B1 - device pci 1c.2 on end # PCIe port B2 - device pci 1c.3 on end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1e.2 on end # audio - device pci 1e.3 on end # modem - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA479M - device apic 0 on end - end - end -end diff --git a/src/mainboard/intel/mtarvon/Options.lb b/src/mainboard/intel/mtarvon/Options.lb deleted file mode 100644 index 7d99620274..0000000000 --- a/src/mainboard/intel/mtarvon/Options.lb +++ /dev/null @@ -1,225 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 as -## published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE = 2 * 1024 * 1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=1 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon" -default CONFIG_MAINBOARD_VENDOR= "Intel" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 - -### -### Coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb deleted file mode 100644 index 5e032487d7..0000000000 --- a/src/mainboard/intel/truxton/Config.lb +++ /dev/null @@ -1,170 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 as -## published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i3100 - device pci_domain 0 on - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - device pci 04.0 on end # ? - device pci 08.0 off end # must be off to boot - device pci 0d.0 off end # must be off to boot - device pci 0d.1 off end # must be off to boot - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1d.0 on end # USB (UHCI) - device pci 1d.7 on end # USB (EHCI) - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - chip superio/smsc/smscsuperio - device pnp 2e.0 off end - device pnp 2e.3 off end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.a off end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # ? - end - end - device apic_cluster 0 on - chip cpu/intel/ep80579 - device apic 0 on end - end - end -end diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb deleted file mode 100644 index dab3f45b77..0000000000 --- a/src/mainboard/intel/truxton/Options.lb +++ /dev/null @@ -1,236 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 as -## published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_RAMTOP -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE = 2 * 1024 * 1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=1 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="Truxton" -default CONFIG_MAINBOARD_VENDOR= "Intel" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680 - -### -### Coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## in order to have coreboot running at 0x100000, RAMTOP has to be set -## -default CONFIG_RAMTOP = 2*1024*1024 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -# Enable the VGA console. -default CONFIG_CONSOLE_VGA=1 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb - -end diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb deleted file mode 100644 index 1f0534c8c0..0000000000 --- a/src/mainboard/intel/xe7501devkit/Config.lb +++ /dev/null @@ -1,174 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FALLBACK_BOOT - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 - -config chip.h - -# based on sample config for tyan/s2735 -chip northbridge/intel/e7501 - device pci_domain 0 on - device pci 0.0 on end # Chipset host controller - device pci 0.1 on end # Host RASUM controller - device pci 2.0 on # Hub interface B - chip southbridge/intel/i82870 # P64H2 - device pci 1c.0 on end # IOAPIC - bus B - device pci 1d.0 on end # Hub to PCI-B bridge - device pci 1e.0 on end # IOAPIC - bus A - device pci 1f.0 on end # Hub to PCI-A bridge - end - end - device pci 3.0 off end # Hub interface C (82808AA connector - disable for now) - device pci 4.0 on # Hub interface D - chip southbridge/intel/i82870 # P64H2 - device pci 1c.0 on end # IOAPIC - bus B - device pci 1d.0 on end # Hub to PCI-B bridge - device pci 1e.0 on end # IOAPIC - bus A - device pci 1f.0 on end # Hub to PCI-A bridge - end - end - device pci 6.0 on end # E7501 Power management registers? (undocumented) - chip southbridge/intel/i82801ca - device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) - device pci 1d.1 off end # USB (not populated) - device pci 1d.2 off end # USB (not populated) - device pci 1e.0 on # Hub to PCI bridge - device pci 0.0 on end - end - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.a off end # ACPI - end - end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC97 Audio - device pci 1f.6 off end # AC97 Modem - end # SB - end # PCI_DOMAIN - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 - device apic 6 on end - end - end -end diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb deleted file mode 100644 index 6968f311af..0000000000 --- a/src/mainboard/intel/xe7501devkit/Options.lb +++ /dev/null @@ -1,238 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAX_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_DEBUG -#uses CONFIG_CPU_OPT - -## These are defined in target Config.lb, don't add here -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_FALLBACK_SIZE -uses COREBOOT_EXTRA_VERSION - -## These are defined in mainboard Config.lb, don't add here -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE - -uses CONFIG_HAVE_HARD_RESET - -default CONFIG_HAVE_HARD_RESET = 1 - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=2097152 -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Build code for the fallback boot? -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=12 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## Build code to export ACPI tables? -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table? -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## CMOS checksum definitions (units == bytes) -## These must match the checksum record in cmos.layout -default CONFIG_LB_CKS_RANGE_START=128 -default CONFIG_LB_CKS_RANGE_END=130 -default CONFIG_LB_CKS_LOC=131 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs, -## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4. -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_LOGICAL_CPUS=0 -default CONFIG_MAX_PHYSICAL_CPUS=2 - -# VGA Console -# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS -# to VGA.rom -default CONFIG_CONSOLE_VGA=0 -default CONFIG_PCI_ROM_RUN=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Motherboard identification -## -default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT" -default CONFIG_MAINBOARD_VENDOR="Intel" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 - -### -### coreboot layout values -### - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## CMOS settings not currently supported due to conflicts with factory BIOS -## -default CONFIG_USE_OPTION_TABLE = 0 - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_DEBUG=1 -# default CONFIG_CPU_OPT="-g" - -### End Options.lb -end diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb deleted file mode 100644 index c5019183dd..0000000000 --- a/src/mainboard/iwill/dk8_htx/Config.lb +++ /dev/null @@ -1,337 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE - object mptable.o -end - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - -#if CONFIG_GENERATE_ACPI_TABLES -# object acpi_tables.o -# object fadt.o -# if CONFIG_SB_HT_CHAIN_ON_BUS0 -# object dsdt_bus0.o -# else -# object dsdt.o -# end -# object ssdt.o -# if CONFIG_ACPI_SSDTX_NUM -# if CONFIG_SB_HT_CHAIN_ON_BUS0 -# object ssdt2_bus0.o -# else -# object ssdt2.o -# end -# end -#end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "mv dsdt_lb.hex dsdt.c" - end - object ./dsdt.o - - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - - if CONFIG_ACPI_SSDTX_NUM - makerule ssdt2.c - depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" - action "mv pci2.hex ssdt2.c" - end - object ./ssdt2.o - makerule ssdt3.c - depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" - action "mv pci3.hex ssdt3.c" - end - object ./ssdt3.o - makerule ssdt4.c - depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" - action "mv pci4.hex ssdt4.c" - end - object ./ssdt4.o - makerule ssdt5.c - depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" - action "mv pci5.hex ssdt5.c" - end - object ./ssdt5.o - end -end - - if CONFIG_USE_INIT - # compile cache_as_ram.c to auto.o - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## - -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -dir /southbridge/amd/amd8132 - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # northbridge - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 - io 0x07 = 0x08ff - io 0x30 = 0x01ff - io 0x2b = 0xd0ff - io 0xf0 = 0xef16 - end - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - - end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - -end - - diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb deleted file mode 100644 index f35afb4f81..0000000000 --- a/src/mainboard/iwill/dk8_htx/Options.lb +++ /dev/null @@ -1,326 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-8K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 8K -default CONFIG_FAILOVER_SIZE=0x02000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 -## extra SSDT num -default CONFIG_ACPI_SSDTX_NUM=3 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0xa - -#real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc4000 -default CONFIG_DCACHE_RAM_SIZE=0x0c000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## for rev F training on AP purpose -## -#default CONFIG_AP_CODE_IN_CAR=1 -#default CONFIG_MEM_TRAIN_SEQ=1 -#default CONFIG_WAIT_BEFORE_CPUS_INIT=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="dk8_htx" -default CONFIG_MAINBOARD_VENDOR="IWILL" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb deleted file mode 100644 index a5fee1b9ee..0000000000 --- a/src/mainboard/iwill/dk8s2/Config.lb +++ /dev/null @@ -1,196 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## ATI Rage XL framebuffering graphics driver -dir /drivers/ati/ragexl - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# config for iwill/dk8s2 -chip northbridge/amd/amdk8/root_complex - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # LDT 0 - chip southbridge/amd/amd8131 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - end - end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end -end - diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb deleted file mode 100644 index 911a54bc2c..0000000000 --- a/src/mainboard/iwill/dk8s2/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE=524288 - -### -### Build options -### - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=12 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=2 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" -default CONFIG_MAINBOARD_VENDOR="ARIMA" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -#default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb deleted file mode 100644 index 478074e0fc..0000000000 --- a/src/mainboard/iwill/dk8x/Config.lb +++ /dev/null @@ -1,171 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627thf - device pnp 2e.0 on end - device pnp 2e.1 on end - device pnp 2e.2 on end - device pnp 2e.3 on end - device pnp 2e.4 on end - device pnp 2e.5 on end - device pnp 2e.6 on end - device pnp 2e.7 on end - device pnp 2e.8 on end - device pnp 2e.9 on end - device pnp 2e.a on end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - end - end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end -end - diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb deleted file mode 100644 index 5cc8161ab1..0000000000 --- a/src/mainboard/iwill/dk8x/Options.lb +++ /dev/null @@ -1,227 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE=524288 - -### -### Build options -### - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=2 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Clean up the motherboard id strings -## -#default CONFIG_MAINBOARD_PART_NUMBER="HDAMA" -#default CONFIG_MAINBOARD_VENDOR="ARIMA" -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f -#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -#default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/jetway/j7f24/Config.lb b/src/mainboard/jetway/j7f24/Config.lb deleted file mode 100644 index 8e0b498067..0000000000 --- a/src/mainboard/jetway/j7f24/Config.lb +++ /dev/null @@ -1,136 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci a.0 on end # Firewire - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end - device apic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC - end - end -end diff --git a/src/mainboard/jetway/j7f24/Options.lb b/src/mainboard/jetway/j7f24/Options.lb deleted file mode 100644 index e65706dbe5..0000000000 --- a/src/mainboard/jetway/j7f24/Options.lb +++ /dev/null @@ -1,96 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_TTYS0_BAUD -uses CONFIG_VIDEO_MB -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_IOAPIC = 1 -default CONFIG_VIDEO_MB = 32 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 10 -default CONFIG_GENERATE_ACPI_TABLES = 0 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_USE_FALLBACK_IMAGE = 1 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -#default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" - -end diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb deleted file mode 100644 index 66ada57c65..0000000000 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ /dev/null @@ -1,270 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Image size calculation -## - -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -driver rtl8168.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" - action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" - action "mv $(CURDIR)/dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/x86/car/cache_as_ram.lds -end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/intel/model_6ex/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i945 - - device apic_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device apic 0 on end - end - end - - device pci_domain 0 on - device pci 00.0 on end # host bridge - # autodetect 0:1.0 because it might or might not be there. - # device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "1" - register "gpe0_en" = "0x00000400" - - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" - - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627thg - device pnp 2e.0 off # Floppy - end - device pnp 2e.1 off # Parport - end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.5 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.7 on # GPIO1, GAME, MIDI - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 - # all default - end - device pnp 2e.9 on # GPIO3/4 - irq 0x30 = 0x03 # does this work? - irq 0xf0 = 0xfb # set inputs/outputs - irq 0xf1 = 0x66 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # HWM - io 0x60 = 0xa00 - irq 0x70 = 0 - end - - end - chip superio/winbond/w83627thg - device pnp 4e.0 off # Floppy - end - device pnp 4e.1 off # Parport - end - device pnp 4e.2 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 11 - end - device pnp 4e.3 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 10 - end - device pnp 4e.5 off # Keyboard - end - device pnp 4e.7 off # GPIO1, GAME, MIDI - end - device pnp 4e.8 off # GPIO2 - end - device pnp 4e.9 off # GPIO3/4 - end - device pnp 4e.a off # ACPI - end - device pnp 4e.b off # HWM - end - end - - end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec - end - end -end diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb deleted file mode 100644 index 811d8efdb3..0000000000 --- a/src/mainboard/kontron/986lcd-m/Options.lb +++ /dev/null @@ -1,328 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -# Tables -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_MAINBOARD_RESOURCES -# SMP -uses CONFIG_SMP -uses CONFIG_LOGICAL_CPUS -uses CONFIG_AP_IN_SIPI_WAIT -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -# Image Size -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -# Payload -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -# Build Internals -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_XIP_ROM_BASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses CONFIG_MMCONF_SUPPORT -uses CONFIG_MMCONF_BASE_ADDRESS -uses CONFIG_GFXUMA - -# -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -# Timers -uses CONFIG_UDELAY_LAPIC -# Console -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_DEBUG -# Toolchain -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -# Tweaks -uses CONFIG_GDB_STUB -uses CONFIG_MAX_REBOOT_CNT -uses CONFIG_USE_WATCHDOG_ON_BOOT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL - -### -### Build options -### - -## -## -default CONFIG_MAX_REBOOT_CNT=3 - -## -## Use the watchdog to break out of a lockup condition -## -default CONFIG_USE_WATCHDOG_ON_BOOT=0 - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## -default CONFIG_UDELAY_LAPIC=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=1 - -## -## Leave a hole for mmapped PCIe config space -## - -default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default CONFIG_MMCONF_SUPPORT=1 -default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 - -## -## UMA -## -default CONFIG_GFXUMA=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=18 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 -default CONFIG_HAVE_ACPI_RESUME=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -# There are some network option roms that don't work with -# coreboot's x86emu. Thus, we only execute the VGA option rom -# for now: -default CONFIG_VGA_ROM_RUN=1 -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_DEBUG=0 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 -default CONFIG_AP_IN_SIPI_WAIT=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024) -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Execute In Place settings -## - -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE ) - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M" -default CONFIG_MAINBOARD_VENDOR= "KONTRON" - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0x10000 - -## -## Use a small 32K stack -## -default CONFIG_STACK_SIZE=0x8000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/kontron/kt690/Config.lb b/src/mainboard/kontron/kt690/Config.lb deleted file mode 100644 index 3cddb5166e..0000000000 --- a/src/mainboard/kontron/kt690/Config.lb +++ /dev/null @@ -1,262 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -#The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - #device pnp 2e.6 off # SPI - #end - device pnp 2e.7 off # GPIO - end - device pnp 2e.8 on # WDTO#, PLED - end - device pnp 2e.9 off # GPIO - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # HWM - io 0x60 = 0xa10 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w83627dhg - #chip superio/smsc/fdc37n972 - # seems this chip is not used? - #end - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0888" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/kontron/kt690/Options.lb b/src/mainboard/kontron/kt690/Options.lb deleted file mode 100644 index 6e3ad131eb..0000000000 --- a/src/mainboard/kontron/kt690/Options.lb +++ /dev/null @@ -1,301 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_VIDEO_MB -uses CONFIG_GFXUMA -uses CONFIG_HAVE_MAINBOARD_RESOURCES - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#256K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 - -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -# BTDC: Only one HT device on Herring. -#HT Unit ID offset -#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="KT690" -default CONFIG_MAINBOARD_VENDOR="KONTRON" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1488 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6900 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 32K stack -## -default CONFIG_STACK_SIZE=0x8000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_VIDEO_MB=1 -default CONFIG_GFXUMA=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -end diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb deleted file mode 100644 index 06147ed82f..0000000000 --- a/src/mainboard/lippert/frontrunner/Config.lb +++ /dev/null @@ -1,112 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/gx2 - device pci_domain 0 on - device pci 0.0 on end - chip southbridge/amd/cs5535 - device pci 12.0 on - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA - end - end - end - - chip cpu/amd/model_gx2 - end - -end - diff --git a/src/mainboard/lippert/frontrunner/Options.lb b/src/mainboard/lippert/frontrunner/Options.lb deleted file mode 100644 index e6a9b48cad..0000000000 --- a/src/mainboard/lippert/frontrunner/Options.lb +++ /dev/null @@ -1,159 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb deleted file mode 100644 index ed6d61eec0..0000000000 --- a/src/mainboard/lippert/roadrunner-lx/Config.lb +++ /dev/null @@ -1,198 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 LiPPERT Embedded Computers GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## Based on Config.lb from AMD's DB800 and DBM690T mainboards. - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - # compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/.rodata/.rom.data/g' -pi $@" - action "perl -e 's/.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary configuration files -## -dir /pc80 -config chip.h - -# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED. -register "sio_gp1x_config" = "0x20" - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES - chip southbridge/amd/cs5536 # Southbridge - # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, - # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 - device pci c.0 on end # IT8888 - device pci e.0 on end # Ethernet - device pci f.0 on # ISA bridge - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - # io 0x64 = 0x1200 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end -end diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb deleted file mode 100644 index b9ca9db796..0000000000 --- a/src/mainboard/lippert/roadrunner-lx/Options.lb +++ /dev/null @@ -1,206 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 LiPPERT Embedded Computers GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## Based on Options.lb from AMD's DB800 mainboard. - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEBUG -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 512 * 1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_VIDEO_MB = 8 -default CONFIG_PCI_ROM_RUN = 0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT = 1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE = 0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET = 0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_PIRQ_ROUTE = 1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE = 0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE = 8 * 1024 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE = 16 * 1024 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250 = 1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD = 115200 -#default CONFIG_TTYS0_BAUD = 57600 -#default CONFIG_TTYS0_BAUD = 38400 -#default CONFIG_TTYS0_BAUD = 19200 -#default CONFIG_TTYS0_BAUD = 9600 -#default CONFIG_TTYS0_BAUD = 4800 -#default CONFIG_TTYS0_BAUD = 2400 -#default CONFIG_TTYS0_BAUD = 1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE = 0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS = 0x3 - -# Compile extra debugging code -default CONFIG_DEBUG = 1 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 - -end diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb deleted file mode 100644 index 8d2052b13e..0000000000 --- a/src/mainboard/lippert/spacerunner-lx/Config.lb +++ /dev/null @@ -1,199 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 LiPPERT Embedded Computers GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## Based on Config.lb from AMD's DB800 and DBM690T mainboards. - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - # compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an ID string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup. -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary configuration files -## -dir /pc80 -config chip.h - -# See also SMC_CONFIG in cache_as_ram_auto.c. -# Bit0 turns off Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. -register "sio_gp1x_config" = "0x01" - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, - # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device - register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 - register "unwanted_vpci[1]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 - device pci c.0 on end # IT8888 - device pci e.0 on end # Ethernet - device pci f.0 on # ISA Bridge - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - io 0x64 = 0x1200 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci f.2 on end # IDE - device pci f.3 off end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end -end diff --git a/src/mainboard/lippert/spacerunner-lx/Options.lb b/src/mainboard/lippert/spacerunner-lx/Options.lb deleted file mode 100644 index 5bb104bf9a..0000000000 --- a/src/mainboard/lippert/spacerunner-lx/Options.lb +++ /dev/null @@ -1,206 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 LiPPERT Embedded Computers GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## Based on Options.lb from AMD's DB800 mainboard. - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEBUG -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 512*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_VIDEO_MB = 8 -default CONFIG_PCI_ROM_RUN = 0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT = 1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE = 0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET = 0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_PIRQ_ROUTE = 1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE = 0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE = 0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE = 0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250 = 1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD = 115200 -#default CONFIG_TTYS0_BAUD = 57600 -#default CONFIG_TTYS0_BAUD = 38400 -#default CONFIG_TTYS0_BAUD = 19200 -#default CONFIG_TTYS0_BAUD = 9600 -#default CONFIG_TTYS0_BAUD = 4800 -#default CONFIG_TTYS0_BAUD = 2400 -#default CONFIG_TTYS0_BAUD = 1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE = 0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS = 0x3 - -# Compile extra debugging code -default CONFIG_DEBUG = 1 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 - -end diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb deleted file mode 100644 index a6480bd585..0000000000 --- a/src/mainboard/mitac/6513wu/Config.lb +++ /dev/null @@ -1,138 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Michael Gold <mgold@ncf.ca> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end - chip southbridge/intel/i82801xx # Southbridge - register "pirqa_routing" = "0x03" - register "pirqb_routing" = "0x05" - register "pirqc_routing" = "0x09" - register "pirqd_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI bridge - device pci 5.0 on end # Audio controller (ESS ES1988) - end - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 10 - end - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 # XXX: not relocatable - io 0x62 = 0x64 # XXX: not relocatable - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 4e.a on # Runtime registers - io 0x60 = 0x400 - end - device pnp 4e.b off end # SMBus - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # Audio controller - device pci 1f.6 off end # Modem - end - end -end diff --git a/src/mainboard/mitac/6513wu/Options.lb b/src/mainboard/mitac/6513wu/Options.lb deleted file mode 100644 index 0dac44bb03..0000000000 --- a/src/mainboard/mitac/6513wu/Options.lb +++ /dev/null @@ -1,108 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Michael Gold <mgold@ncf.ca> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CC -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_VGA -uses CONFIG_CROSS_COMPILE -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_FALLBACK_SIZE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_HEAP_SIZE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_OBJCOPY -uses CONFIG_PCI_ROM_RUN -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_INIT -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_VIDEO_MB -uses CONFIG_XIP_ROM_BASE -uses CONFIG_XIP_ROM_SIZE -uses COREBOOT_EXTRA_VERSION -uses HOSTCC - -# Motherboard info, tables, etc. -default CONFIG_MAINBOARD_VENDOR = "Mitac" -default CONFIG_MAINBOARD_PART_NUMBER = "6513WU" -default CONFIG_IRQ_SLOT_COUNT = 8 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_USE_OPTION_TABLE = 0 - -# ROM layout -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_ROM_PAYLOAD = 1 - -# RAM layout -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 - -# Misc. settings -default CONFIG_USE_INIT = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 - -# Compiler setup -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" - -# Console settings -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7 # No debugging/spew -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 - -# Enable onboard video -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_VIDEO_MB = 1 - -end diff --git a/src/mainboard/msi/ms6119/Config.lb b/src/mainboard/msi/ms6119/Config.lb deleted file mode 100644 index 79bc904d64..0000000000 --- a/src/mainboard/msi/ms6119/Config.lb +++ /dev/null @@ -1,133 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/msi/ms6119/Options.lb b/src/mainboard/msi/ms6119/Options.lb deleted file mode 100644 index 7930819f12..0000000000 --- a/src/mainboard/msi/ms6119/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/msi/ms6147/Config.lb b/src/mainboard/msi/ms6147/Config.lb deleted file mode 100644 index 73f79cbef1..0000000000 --- a/src/mainboard/msi/ms6147/Config.lb +++ /dev/null @@ -1,141 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -mainboardinit arch/i386/lib/cpu_reset.inc - -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 off # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/msi/ms6147/Options.lb b/src/mainboard/msi/ms6147/Options.lb deleted file mode 100644 index e6ccb87bd8..0000000000 --- a/src/mainboard/msi/ms6147/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/msi/ms6156/Config.lb b/src/mainboard/msi/ms6156/Config.lb deleted file mode 100644 index 0a93cc772e..0000000000 --- a/src/mainboard/msi/ms6156/Config.lb +++ /dev/null @@ -1,134 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 off # GPIO 1 - end - device pnp 3f0.8 off # GPIO 2 - end - device pnp 3f0.9 off # GPIO 3 - end - device pnp 3f0.a off # ACPI - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - device pci 14.0 on end # Onboard audio (Ensoniq ES1371) - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/msi/ms6156/Options.lb b/src/mainboard/msi/ms6156/Options.lb deleted file mode 100644 index 8d6de68a61..0000000000 --- a/src/mainboard/msi/ms6156/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_MAINBOARD_VENDOR = "MSI" -default CONFIG_MAINBOARD_PART_NUMBER = "MS-6156" -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb deleted file mode 100644 index 3f77f30555..0000000000 --- a/src/mainboard/msi/ms6178/Config.lb +++ /dev/null @@ -1,133 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 (only header on board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.6 off end # Consumer IR (TODO) - device pnp 2e.7 on # Game port / MIDI / GPIO 1 - io 0x60 = 0x201 - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 2e.8 on end # GPIO 2 - device pnp 2e.9 on end # GPIO 3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 on end # AC'97 modem - end - end -end - diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb deleted file mode 100644 index 04660f0c55..0000000000 --- a/src/mainboard/msi/ms6178/Options.lb +++ /dev/null @@ -1,99 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_WRITE_HIGH_TABLES -uses CONFIG_VIDEO_MB - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 4 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_WRITE_HIGH_TABLES = 1 -default CONFIG_VIDEO_MB = 1 -end diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb deleted file mode 100644 index adc58a9a11..0000000000 --- a/src/mainboard/msi/ms7135/Config.lb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/ati/ragexl - -# Needed by irq_tables and mptable and acpi_tables. -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE - object mptable.o -end - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -## -## Build our 16 bit and 32 bit coreboot entry code. -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (this is where coreboot is entered). -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an ID string (for safe flashing). -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for CK804 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup. -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_754 # Socket 754 CPU - device apic 0 on end # APIC - end - end - - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thf # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5 - device pnp 4e.8 off end # GPIO 2 - device pnp 4e.9 off end # GPIO 3, GPIO 4 - device pnp 4e.a off end # ACPI - device pnp 4e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 1.1 on end # SMbus - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI) -- not wired out - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 -- not wired out - device pci c.0 off end # PCI E 2 -- not wired out - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb deleted file mode 100644 index b3b2b4beaf..0000000000 --- a/src/mainboard/msi/ms7135/Options.lb +++ /dev/null @@ -1,321 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_AP_CODE_IN_CAR -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_MEM_TRAIN_SEQ -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_ID_SECTION_OFFSET - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## ---> 512 Kbytes -default CONFIG_ROM_SIZE=(512*1024) - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=(4*1024) - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=13 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -#default CONFIG_DCACHE_RAM_BASE=0xcf000 -#default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 - -## APIC stuff -#default CONFIG_ENABLE_APIC_EXT_ID=0 -#default CONFIG_APIC_ID_OFFSET=0x10 -#default CONFIG_LIFT_BSP_APIC_ID=0 - - -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" -default CONFIG_MAINBOARD_VENDOR="MSI" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb deleted file mode 100644 index f420731f42..0000000000 --- a/src/mainboard/msi/ms7260/Config.lb +++ /dev/null @@ -1,288 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -driver mainboard.o -object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables). -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -# ROMSTRAP table for MCP55. -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - mainboardinit cpu/amd/car/cache_as_ram.inc - -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # Northbridge / mc0 - device pci 18.0 on - # Devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 / IrDA - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ - irq 0x72 = 12 # PS/2 mouse IRQ - end - device pnp 4e.6 off # Serial flash interface - # io 0x62 = 0x100 - end - device pnp 4e.7 off # GPIO1/6, game port, MIDI port - # io 0x60 = 0x220 # Datasheet: 0x201 - # io 0x62 = 0x300 # Datasheet: 0x330 - # irq 0x70 = 9 - end - device pnp 4e.8 off # WDTO#, PLED - end - device pnp 4e.9 off # GPIO2/3/4/5, SUSLED - end - device pnp 4e.a off # ACPI - end - device pnp 4e.b on # HWM (for lm-sensors) - io 0x60 = 0xa10 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - # TODO: Needed? - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end - end - # TODO: Check if the stuff below is correct / needed. - device pci 1.1 on # SM 1 - # PCI device SMBus address will depend on addon PCI device, - # do we need to scan_smbus_bus? - - # chip drivers/generic/generic # PCIXA Slot1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB Slot1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB Slot2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI Slot1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 off end # SATA 2 (N/A on this board) - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A on this board) - device pci a.0 off end # PCI E 5 (N/A on this board?) - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # TODO: Check the two lines below. - register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end - -# TODO -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end - -end diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb deleted file mode 100644 index 1be372ae6c..0000000000 --- a/src/mainboard/msi/ms7260/Options.lb +++ /dev/null @@ -1,188 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER # ? -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT -uses CONFIG_SERIAL_CPU_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_RAMTOP -uses CONFIG_AP_CODE_IN_CAR -uses CONFIG_MEM_TRAIN_SEQ -uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_ID_SECTION_OFFSET - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 -default CONFIG_RAMTOP = 2048*1024 # 1MB more for pgtbl. -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct. -default CONFIG_GENERATE_MP_TABLE = 1 # TODO: Check if correct. -default CONFIG_HAVE_OPTION_TABLE = 1 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -# default CONFIG_SERIAL_CPU_INIT = 0 -default CONFIG_ENABLE_APIC_EXT_ID = 0 -default CONFIG_APIC_ID_OFFSET = 0x10 -default CONFIG_LIFT_BSP_APIC_ID = 1 - -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 - -# Memory hole size. 0 means disable, others will enable the hole. In that -# case, if it is smaller than mmio_basek, it will use mmio_basek instead. -# default CONFIG_HW_MEM_HOLE_SIZEK = 0x200000 # 2GB -default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # 1GB -# default CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 # 512MB - -# Make auto increase hole size to avoid hole_startk equal to basek so as -# to make some kernel happy. -# default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 1 - -# Opteron K8 1G HT support. -default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 - -# HT Unit ID offset, default is 1, the typical one, 0 means only one HT device. -default CONFIG_HT_CHAIN_UNITID_BASE = 0 - -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 - -# Make the SB HT chain on bus 0, default is not (0). -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 - -# Only offset for SB chain? Default is yes (1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 - -# Allow capable device use that above 4GB. -# default CONFIG_PCI_64BIT_PREF_MEM = 1 - -default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. -default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default CONFIG_USBDEBUG_DIRECT = 0 -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 -default CONFIG_USE_INIT = 0 -default CONFIG_AP_CODE_IN_CAR = 0 -default CONFIG_MEM_TRAIN_SEQ = 2 -default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)" -default CONFIG_MAINBOARD_VENDOR = "MSI" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE -default CONFIG_STACK_SIZE = 0x2000 -default CONFIG_HEAP_SIZE = 0x8000 -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) -default CONFIG_RAMBASE = 0x00100000 -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_USE_PRINTK_IN_CAR = 1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -default CONFIG_ID_SECTION_OFFSET=0x80 - -end diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb deleted file mode 100644 index c3bddcfe1f..0000000000 --- a/src/mainboard/msi/ms9185/Config.lb +++ /dev/null @@ -1,231 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 AMD -## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. -## -## Copyright (C) 2006 MSI -## Written by bxshi <bingxunshi@gmail.com> for MSI. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE - object mptable.o -end - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - if CONFIG_USE_INIT - # compile cache_as_ram.c to auto.o - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end -## -## Build our 16 bit and 32 bit coreboot entry code -## - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for amd/serengeti_cheetah -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - device pci e.1 on end # SATA 0x024a bx_a001 - device pci e.2 on end # SATA 0x024a bx_a001 - device pci e.3 on end # SATA 0x024a bx_a001 - end - device pci 1.0 on # Legacy pci main 0x0205 - end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end - end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # it is in bcm5785_0 bus - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # amdk8 - end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - -end - - diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb deleted file mode 100644 index d3423f59e1..0000000000 --- a/src/mainboard/msi/ms9185/Options.lb +++ /dev/null @@ -1,327 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 AMD -## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. -## -## Copyright (C) 2006 MSI -## Written by bxshi <bingxunshi@gmail.com> for MSI. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -#default CONFIG_GENERATE_ACPI_TABLES=1 -## extra SSDT num -#default CONFIG_ACPI_SSDTX_NUM=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x8 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x06 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcc000 -default CONFIG_DCACHE_RAM_SIZE=0x04000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="MS9185" -default CONFIG_MAINBOARD_VENDOR="MSI" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb deleted file mode 100644 index ec1211e7b4..0000000000 --- a/src/mainboard/msi/ms9282/Config.lb +++ /dev/null @@ -1,322 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 AMD -## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. -## -## Copyright (C) 2006 MSI -## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/ati/ragexl -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds -end - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - - -# sample config for msi/ms9282 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SERIAL_FALSH - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 70 on #0 pca9554 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 57 on end - end - end - device i2c 70 on #0 pca9554 2 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 57 on end - end - end - end - end - device pci 1.1 on # SM 1 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 72 on #pca9554 channle1 - chip drivers/i2c/adm1027 #HWM ADT7476 1 - device i2c 2e on end - end - end - device i2c 72 on #pca9545 channel 2 - chip drivers/i2c/adm1027 #HWM ADT7463 - device i2c 2e on end - end - end - device i2c 72 on end #pca9545 channel 3 - device i2c 72 on #pca9545 channel 4 - chip drivers/i2c/adm1027 #HWM ADT7476 2 - device i2c 2e on end - end - end - end - end - - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on #P2P - device pci 4.0 on end - end # P2P - device pci 7.0 on end # reserve - device pci 8.0 on end # MAC0 - device pci 9.0 on end # MAC1 - device pci a.0 on - device pci 0.0 on - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end - end # 0x376 - device pci b.0 on end # PCI E 0x374 - device pci c.0 on end - device pci d.0 on #SAS - device pci 0.0 on end - end # PCI E 1 0x378 - device pci e.0 on end # PCI E 0 0x375 - device pci f.0 on end #PCI E 0x377 pci_E slot - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #mc0 - - end # pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end -# device pnp 0.4 off end -# device pnp 0.5 on end -# end -end # root_complex diff --git a/src/mainboard/msi/ms9282/Options.lb b/src/mainboard/msi/ms9282/Options.lb deleted file mode 100644 index ee8be01679..0000000000 --- a/src/mainboard/msi/ms9282/Options.lb +++ /dev/null @@ -1,311 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 AMD -## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. -## -## Copyright (C) 2006 MSI -## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -#bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -#bx_b005+ -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -# stepan 2007-04-12 -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ID_SECTION_OFFSET - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default CONFIG_ROM_SIZE=524288 - -#1M bytes -#bx- default CONFIG_ROM_SIZE=1048576 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 - -#make the SB HT chain on bus 0, default is not (0) -#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2 - -##bx_b005+ make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -##only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#VGA -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcc000 -default CONFIG_DCACHE_RAM_SIZE=0x4000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="ms9282" -default CONFIG_MAINBOARD_VENDOR="MSI" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb deleted file mode 100644 index e63b1475dd..0000000000 --- a/src/mainboard/nec/powermate2000/Config.lb +++ /dev/null @@ -1,123 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off end # Com2 (N/A) - device pnp 2e.7 on # PS/2 keyboard - irq 0x70 = 1 - irq 0x72 = 0 - end - device pnp 2e.9 off end # Game port (N/A) - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x800 - end - device pnp 2e.b on # MIDI port - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end - diff --git a/src/mainboard/nec/powermate2000/Options.lb b/src/mainboard/nec/powermate2000/Options.lb deleted file mode 100644 index 735f30c7de..0000000000 --- a/src/mainboard/nec/powermate2000/Options.lb +++ /dev/null @@ -1,96 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 5 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb deleted file mode 100644 index f053e669a9..0000000000 --- a/src/mainboard/newisys/khepri/Config.lb +++ /dev/null @@ -1,192 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end - - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 - chip southbridge/amd/amd8131 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 on end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 on end - device pci 1.6 on end - end - end # LDT1 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end -end - diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb deleted file mode 100644 index ad54dc6037..0000000000 --- a/src/mainboard/newisys/khepri/Options.lb +++ /dev/null @@ -1,243 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="Khepri" -default CONFIG_MAINBOARD_VENDOR="Newisys" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb deleted file mode 100644 index ba30037815..0000000000 --- a/src/mainboard/nvidia/l1_2pvv/Config.lb +++ /dev/null @@ -1,373 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" - action "mv dsdt_lb.hex dsdt.c" - end - object ./dsdt.o - - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - - if CONFIG_ACPI_SSDTX_NUM - makerule ssdt6.c - depends "$(CONFIG_MAINBOARD)/dx/pci6.asl" - action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex" - action "mv pci6.hex ssdt6.c" - end - object ./ssdt6.o - makerule ssdt5.c - depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" - action "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" - action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" - action "mv pci5.hex ssdt5.c" - end - object ./ssdt5.o - end -end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb deleted file mode 100644 index 00efb92b09..0000000000 --- a/src/mainboard/nvidia/l1_2pvv/Options.lb +++ /dev/null @@ -1,353 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 -#default CONFIG_ROM_SIZE=0x100000 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#default CONFIG_USBDEBUG_DIRECT=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default CONFIG_MEM_TRAIN_SEQ=1 -default CONFIG_WAIT_BEFORE_CPUS_INIT=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="l1_2pvv" -default CONFIG_MAINBOARD_VENDOR="NVIDIA" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/olpc/btest/Config.lb b/src/mainboard/olpc/btest/Config.lb deleted file mode 100644 index 9edcbd066b..0000000000 --- a/src/mainboard/olpc/btest/Config.lb +++ /dev/null @@ -1,139 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/gx2 - register "irqmap" = "0xaa5b" - register "setupflash" = "0" - device apic_cluster 0 on - chip cpu/amd/model_gx2 - device apic 0 on end - end - end - device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. - # Frame Pulse Width = 4clocks - # IRQ Data Frames = 17Frames - # SIRQ Mode = continous , It would be better if the EC could operate in - # Active(Quiet) mode. Save power.... - # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - #register "lpc_irq" = "0x00001002" - #register "lpc_serirq_enable" = "0xEFFD0080" - #register "enable_gpio0_inta" = "1" - #register "enable_ide_nand_flash" = "1" - #register "enable_uarta" = "1" - #register "enable_USBP4_host" = "1" - #register "audio_irq" = "5" - #register "usbf4_irq" = "10" - #register "usbf5_irq" = "10" - #register "usbf6_irq" = "0" - #register "usbf7_irq" = "0" - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC - register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG - register "unwanted_vpci[2]" = "0" # End of list has a zero - end - end -end - diff --git a/src/mainboard/olpc/btest/Options.lb b/src/mainboard/olpc/btest/Options.lb deleted file mode 100644 index ab05e04e5c..0000000000 --- a/src/mainboard/olpc/btest/Options.lb +++ /dev/null @@ -1,160 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb deleted file mode 100644 index 9edcbd066b..0000000000 --- a/src/mainboard/olpc/rev_a/Config.lb +++ /dev/null @@ -1,139 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/gx2 - register "irqmap" = "0xaa5b" - register "setupflash" = "0" - device apic_cluster 0 on - chip cpu/amd/model_gx2 - device apic 0 on end - end - end - device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. - # Frame Pulse Width = 4clocks - # IRQ Data Frames = 17Frames - # SIRQ Mode = continous , It would be better if the EC could operate in - # Active(Quiet) mode. Save power.... - # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - #register "lpc_irq" = "0x00001002" - #register "lpc_serirq_enable" = "0xEFFD0080" - #register "enable_gpio0_inta" = "1" - #register "enable_ide_nand_flash" = "1" - #register "enable_uarta" = "1" - #register "enable_USBP4_host" = "1" - #register "audio_irq" = "5" - #register "usbf4_irq" = "10" - #register "usbf5_irq" = "10" - #register "usbf6_irq" = "0" - #register "usbf7_irq" = "0" - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC - register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG - register "unwanted_vpci[2]" = "0" # End of list has a zero - end - end -end - diff --git a/src/mainboard/olpc/rev_a/Options.lb b/src/mainboard/olpc/rev_a/Options.lb deleted file mode 100644 index ab05e04e5c..0000000000 --- a/src/mainboard/olpc/rev_a/Options.lb +++ /dev/null @@ -1,160 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb deleted file mode 100644 index 38da7398b4..0000000000 --- a/src/mainboard/pcengines/alix1c/Config.lb +++ /dev/null @@ -1,190 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006-2007 Ronald G. Minnich <rminnich@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - - #compile cache_as_ram.c to auto.inc - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -# mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc - - mainboardinit cpu/amd/model_lx/cache_as_ram.inc - mainboardinit ./cache_as_ram_auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - # How to get these? Boot linux and do this: - # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x0000105a" - # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EFA5" - # mode is high 10 bits (determined from code) - register "lpc_serirq_mode" = "1" - # Don't yet know how to find this. - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3F8" - register "com1_irq" = "4" - register "com2_enable" = "0" - register "com2_address" = "0x2F8" - register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 on end # GPIO2 - device pnp 2e.9 on end # GPIO3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci f.1 on end # Flash controller - device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end - -end - diff --git a/src/mainboard/pcengines/alix1c/Options.lb b/src/mainboard/pcengines/alix1c/Options.lb deleted file mode 100644 index 37fa14a317..0000000000 --- a/src/mainboard/pcengines/alix1c/Options.lb +++ /dev/null @@ -1,198 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006-2007 Ronald G. Minnich <rminnich@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 512*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_VIDEO_MB=8 -default CONFIG_PCI_ROM_RUN=0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=5 -default CONFIG_PIRQ_ROUTE=1 -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -end diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb deleted file mode 100644 index 648be3427f..0000000000 --- a/src/mainboard/rca/rm4100/Config.lb +++ /dev/null @@ -1,144 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/intel/i82830 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x06" - register "pirqc_routing" = "0x07" - register "pirqd_routing" = "0x09" - register "pirqe_routing" = "0x0a" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1d.0 on end # USB UHCI Controller #1 - device pci 1d.1 on end # USB UHCI Controller #2 - device pci 1d.2 on end # USB UHCI Controller #3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on # PCI bridge - device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet - end - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # Com2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.9 off end # Game port - device pnp 2e.a on # PME - io 0x60 = 0x800 - end - device pnp 2e.b off end # MPU-401 - end - end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 on end # AC'97 modem - end - end - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # Mobile Celeron Micro-FCBGA Socket 479 - device apic 0 on end # APIC - end - end -end - diff --git a/src/mainboard/rca/rm4100/Options.lb b/src/mainboard/rca/rm4100/Options.lb deleted file mode 100644 index c9b28ce388..0000000000 --- a/src/mainboard/rca/rm4100/Options.lb +++ /dev/null @@ -1,96 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CC -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_VGA -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_IOAPIC -uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE -uses CONFIG_PCI_ROM_RUN -uses CONFIG_ROM_PAYLOAD -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_UDELAY_TSC -uses CONFIG_VIDEO_MB -uses CONFIG_CROSS_COMPILE -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_FALLBACK_SIZE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_HEAP_SIZE -uses HOSTCC -uses CONFIG_IRQ_SLOT_COUNT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_OBJCOPY -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_LCS -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_GENERATE_ACPI_TABLES = 0 -default CONFIG_IOAPIC = 0 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 -default CONFIG_VIDEO_MB = 0 -default CONFIG_STACK_SIZE = 0x2000 -default CONFIG_HEAP_SIZE = 0x4000 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_ROM_PAYLOAD = 1 -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAINBOARD_VENDOR = "RCA" -default CONFIG_MAINBOARD_PART_NUMBER = "RM4100" -end diff --git a/src/mainboard/roda/rk886ex/Config.lb b/src/mainboard/roda/rk886ex/Config.lb deleted file mode 100644 index 259eb31a3c..0000000000 --- a/src/mainboard/roda/rk886ex/Config.lb +++ /dev/null @@ -1,237 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Image size calculation -## - -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -driver rtl8168.o -object ec.o -object m3885.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" - action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" - action "mv $(CURDIR)/dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/x86/car/cache_as_ram.lds -end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/intel/model_6ex/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i945 - - device apic_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device apic 0 on end - end - end - - device pci_domain 0 on - device pci 00.0 on end # host bridge - # auto detection: - #device pci 01.0 off end # i945 PCIe root port - #device pci 02.0 on end # vga controller - #device pci 02.1 on end # display controller - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi8_routing" = "1" - register "gpi7_routing" = "2" - register "gpe0_en" = "0x20800007" - - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" - - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on - chip southbridge/ti/pci7420 - register "smartcard_enabled" = "0x0" - device pci 3.0 on end - device pci 3.1 on end - device pci 3.2 on end - device pci 3.3 off end # smartcard - end - end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47n227 - device pnp 2e.1 off # Parallel port - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # Keyboard+Mouse - # io 0x60 = 0x60 - # io 0x62 = 0x64 - # irq 0x70 = 1 - # irq 0x72 = 12 - end - end - chip superio/renesas/m3885x - device pnp ff.1 on # dummy address - end - end - - end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec - end - end -end diff --git a/src/mainboard/roda/rk886ex/Options.lb b/src/mainboard/roda/rk886ex/Options.lb deleted file mode 100644 index 735223272c..0000000000 --- a/src/mainboard/roda/rk886ex/Options.lb +++ /dev/null @@ -1,339 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -# Tables -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_MAINBOARD_RESOURCES -uses CONFIG_HAVE_ACPI_RESUME -# SMP -uses CONFIG_SMP -uses CONFIG_LOGICAL_CPUS -uses CONFIG_AP_IN_SIPI_WAIT -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -# Image Size -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -# Payload -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -# Build Internals -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_XIP_ROM_BASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses CONFIG_MMCONF_SUPPORT -uses CONFIG_MMCONF_BASE_ADDRESS -uses CONFIG_GFXUMA -# -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -# Timers -uses CONFIG_UDELAY_LAPIC -# Console -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_PCI_OPTION_ROM_RUN_YABEL -uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE -uses CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES -uses CONFIG_DEBUG -# Toolchain -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -# Tweaks -uses CONFIG_GDB_STUB -uses CONFIG_MAX_REBOOT_CNT -uses CONFIG_USE_WATCHDOG_ON_BOOT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL - -### -### Build options -### - -## -## -default CONFIG_MAX_REBOOT_CNT=3 - -## -## Use the watchdog to break out of a lockup condition -## -default CONFIG_USE_WATCHDOG_ON_BOOT=0 - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## -default CONFIG_UDELAY_LAPIC=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=1 - -## -## Leave a hole for mmapped PCIe config space -## - -default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default CONFIG_MMCONF_SUPPORT=1 -default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 - -## -## UMA -## -default CONFIG_GFXUMA=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=18 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 -default CONFIG_HAVE_ACPI_RESUME=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default CONFIG_coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=0 -default CONFIG_PCI_ROM_RUN=0 -#default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 -#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0 -# This is needed for Intel's IGD design: -#default CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=1 -#default CONFIG_DEBUG=0 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 -default CONFIG_AP_IN_SIPI_WAIT=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024) -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Execute In Place settings -## - -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE ) - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="RK886EX" -default CONFIG_MAINBOARD_VENDOR= "RODA" - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x4352 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6886 - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 32K stack -## -default CONFIG_STACK_SIZE=0x8000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=1 - -## -## USB debug console -## - -default CONFIG_USBDEBUG_DIRECT=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb deleted file mode 100644 index cdf4b58932..0000000000 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb +++ /dev/null @@ -1,126 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 370.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 370.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 370.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 370.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 370.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 370.6 on # PS/2 mouse - irq 0x70 = 12 - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb b/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb deleted file mode 100644 index 61b24fc566..0000000000 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb +++ /dev/null @@ -1,96 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -end diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb deleted file mode 100644 index 2781be8d77..0000000000 --- a/src/mainboard/sunw/ultra40/Config.lb +++ /dev/null @@ -1,256 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for CK804 -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2895 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end # link 0 - device pci 18.0 on # link1 - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47m10x - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master CK804 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave CK804 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # link 2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - chip northbridge/amd/amdk8 - device pci 19.0 on end # link 0 - device pci 19.0 on - # devices on link 1, link 1 == LDT 1 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end # device pci 19.0 - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end # PCI domain - -end #root_complex diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb deleted file mode 100644 index e820fd03f8..0000000000 --- a/src/mainboard/sunw/ultra40/Options.lb +++ /dev/null @@ -1,280 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_ID_SECTION_OFFSET - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -#default CONFIG_ROM_SIZE=524288 - -#1M bytes -default CONFIG_ROM_SIZE=1048576 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#VGA -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="ultra40" -default CONFIG_MAINBOARD_VENDOR="sunw" - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb deleted file mode 100644 index 18cde515db..0000000000 --- a/src/mainboard/supermicro/h8dme/Config.lb +++ /dev/null @@ -1,301 +0,0 @@ -## -## This file is part of the coreboot project. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 - device i2c 48 off end - device i2c 49 off end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb deleted file mode 100644 index 85d8331701..0000000000 --- a/src/mainboard/supermicro/h8dme/Options.lb +++ /dev/null @@ -1,355 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_HAVE_LOW_TABLES -uses CONFIG_MULTIBOOT -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -#default CONFIG_ROM_SIZE=524288 -default CONFIG_ROM_SIZE=0x100000 - -default CONFIG_HAVE_LOW_TABLES = 0 -default CONFIG_MULTIBOOT=0 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=1 -default CONFIG_MEM_TRAIN_SEQ=1 -default CONFIG_WAIT_BEFORE_CPUS_INIT=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="h8dme" -default CONFIG_MAINBOARD_VENDOR="Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb deleted file mode 100644 index 13db09a54d..0000000000 --- a/src/mainboard/supermicro/h8dmr/Config.lb +++ /dev/null @@ -1,323 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb deleted file mode 100644 index f0e9082663..0000000000 --- a/src/mainboard/supermicro/h8dmr/Options.lb +++ /dev/null @@ -1,353 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -#default CONFIG_ROM_SIZE=524288 -default CONFIG_ROM_SIZE=0x100000 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use -## -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default CONFIG_MEM_TRAIN_SEQ=1 -default CONFIG_WAIT_BEFORE_CPUS_INIT=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="h8dmr" -default CONFIG_MAINBOARD_VENDOR="Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0xf000 - - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_USE_FAILOVER_IMAGE=0 -default CONFIG_USE_FALLBACK_IMAGE=0 -default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/supermicro/h8dmr_fam10/Config.lb b/src/mainboard/supermicro/h8dmr_fam10/Config.lb deleted file mode 100644 index fe2d1b6ff8..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/Config.lb +++ /dev/null @@ -1,333 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -# for testing with -O != s. FIXME -#default CONFIG_XIP_ROM_SIZE = 128 * 1024 -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -dir /southbridge/nvidia/mcp55 - -chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F_1207 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # SB on link 2.0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb deleted file mode 100644 index a7d3ca8095..0000000000 --- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb +++ /dev/null @@ -1,363 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_UNCOMPRESSED - -uses CONFIG_PCI_BUS_SEGN_BITS - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_AMDMCT - -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_AMD_UCODE_PATCH_FILE -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x02000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=16384*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x00 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=1 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc4000 -default CONFIG_DCACHE_RAM_SIZE=0x0c000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 -default CONFIG_USE_INIT=0 - -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 -default CONFIG_AMDMCT = 1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="h8dmr (Fam10)" -default CONFIG_MAINBOARD_VENDOR="Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 - -## -## Set microcode patch file name -## -## Barcelona rev Ax: "mc_patch_01000020.h" -## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" -## Barcelona rev B2, B3: "mc_patch_01000083.h" -## Shanghai rev RB-C2: "mc_patch_01000086.h" -## Shanghai rev DA-C2: "mc_patch_0100009f.h" -## -#default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000086.h" -default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h" - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0x1e000 - -## -## Use a 32K stack -## -default CONFIG_STACK_SIZE=0x8000 - -## -## Use a 48K heap -## -default CONFIG_HEAP_SIZE=0xc0000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00200000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -# CBFS will take care of payload compression -default CONFIG_UNCOMPRESSED = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_USE_FAILOVER_IMAGE=0 -default CONFIG_USE_FALLBACK_IMAGE=0 -default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - -default CONFIG_ID_SECTION_OFFSET=0x80 -### End Options.lb -end diff --git a/src/mainboard/supermicro/h8qme_fam10/Config.lb b/src/mainboard/supermicro/h8qme_fam10/Config.lb deleted file mode 100644 index 863575b210..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/Config.lb +++ /dev/null @@ -1,347 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -# for testing with -O != s. FIXME -#default CONFIG_XIP_ROM_SIZE = 128 * 1024 -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -dir /southbridge/nvidia/mcp55 -dir /southbridge/amd/amd8132 - -chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F_1207 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # SB on link 2.0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic #dimm 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic #dimm 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic #dimm 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic #dimm 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic #dimm 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic #dimm 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic #dimm 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic #dimm 1-1-1 - # device i2c 57 on end - # end - # chip drivers/generic/generic #dimm 2-0-0 - # device i2c 58 on end - # end - # chip drivers/generic/generic #dimm 2-0-1 - # device i2c 59 on end - # end - # chip drivers/generic/generic #dimm 2-1-0 - # device i2c 5a on end - # end - # chip drivers/generic/generic #dimm 2-1-1 - # device i2c 5b on end - # end - # chip drivers/generic/generic #dimm 3-0-0 - # device i2c 5c on end - # end - # chip drivers/generic/generic #dimm 3-0-1 - # device i2c 5d on end - # end - # chip drivers/generic/generic #dimm 3-1-0 - # device i2c 5e on end - # end - # chip drivers/generic/generic #dimm 3-1-1 - # device i2c 5f on end - # end - - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will diepend on addon pci device, do we need to scan_smbus_bus? -# - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - end #amd8132 - end #device pci 19.0 - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex diff --git a/src/mainboard/supermicro/h8qme_fam10/Options.lb b/src/mainboard/supermicro/h8qme_fam10/Options.lb deleted file mode 100644 index 279d8ac96e..0000000000 --- a/src/mainboard/supermicro/h8qme_fam10/Options.lb +++ /dev/null @@ -1,373 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_VGA -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_UNCOMPRESSED - -uses CONFIG_PCI_BUS_SEGN_BITS - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_AMDMCT - -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_AMD_UCODE_PATCH_FILE -uses CONFIG_ID_SECTION_OFFSET - -uses CONFIG_PIRQ_ROUTE - -default CONFIG_PIRQ_ROUTE = 1 - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x02000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=16384*1024 -#default CONFIG_RAMTOP=16384*8192 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_PHYSICAL_CPUS=4 -default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=1 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x00 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#VGA Console -default CONFIG_VGA=0 -default CONFIG_CONSOLE_VGA=1 -default CONFIG_VGA_ROM_RUN=1 -default CONFIG_PCI_ROM_RUN=0 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=1 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc4000 -default CONFIG_DCACHE_RAM_SIZE=0x0c000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 -default CONFIG_USE_INIT=0 - -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 -default CONFIG_AMDMCT = 1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="h8qme (Fam10)" -default CONFIG_MAINBOARD_VENDOR="Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511 - -## -## Set microcode patch file name -## -## Barcelona rev Ax: "mc_patch_01000020.h" -## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" -## Barcelona rev B2, B3: "mc_patch_01000083.h" -## Shanghai rev RB-C2: "mc_patch_01000086.h" -## Shanghai rev DA-C2: "mc_patch_0100009f.h" -## -#default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000086.h" -default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h" - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0x1e000 - -## -## Use a 64K stack -## -default CONFIG_STACK_SIZE=0x10000 - -## -## Use a 48K heap -## -default CONFIG_HEAP_SIZE=0xc000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00200000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -# CBFS will take care of payload compression -default CONFIG_UNCOMPRESSED = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -#default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_USE_FAILOVER_IMAGE=0 -default CONFIG_USE_FALLBACK_IMAGE=0 -default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - -default CONFIG_ID_SECTION_OFFSET=0x80 -### End Options.lb -end diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb deleted file mode 100644 index 17096f5da4..0000000000 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ /dev/null @@ -1,167 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7525 # mch - device pci_domain 0 on - chip southbridge/intel/esb6300 # esb6300 - register "pirq_a_d" = "0x0b0a0a05" - register "pirq_e_h" = "0x0a0b0c80" - - device pci 1c.0 on end - - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.4 on end - device pci 1d.5 on end - device pci 1d.7 on end - - device pci 1e.0 on end - - device pci 1f.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.9 off end - device pnp 2e.a on end - device pnp 2e.b off end - device pnp 2e.f off end - device pnp 2e.10 off end - device pnp 2e.14 off end - end - end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 on end - end - device pci 00.0 on end - device pci 00.1 on end - device pci 00.2 on end - device pci 02.0 on end - device pci 03.0 on end - device pci 04.0 on end - device pci 08.0 on end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu1 - device apic 6 on end - end - end -end - diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb deleted file mode 100644 index 626f0bebb3..0000000000 --- a/src/mainboard/supermicro/x6dai_g/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DAI" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb deleted file mode 100644 index 866042b548..0000000000 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ /dev/null @@ -1,190 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 # MCH - chip drivers/generic/debug # DEBUGGING - device pnp 00.0 on end - device pnp 00.1 off end - device pnp 00.2 off end - device pnp 00.3 off end - end - device pci_domain 0 on - chip southbridge/intel/esb6300 # ESB6300 - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1c.0 on - chip drivers/generic/generic - device pci 01.0 on end # onboard gige1 - device pci 02.0 on end # onboard gige2 - end - end - - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.4 on end # Southbridge Watchdog timer - device pci 1d.5 on end # Southbridge I/O apic1 - device pci 1d.7 on end - - # VGA / PCI 32-bit - device pci 1e.0 on - chip drivers/generic/generic - device pci 01.0 on end - end - end - - - device pci 1f.0 on # ISA bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.9 off end - device pnp 2e.a on end - device pnp 2e.b off end - end - end - device pci 1f.1 on end - device pci 1f.2 off end - device pci 1f.3 on end # SMBus - device pci 1f.5 off end - device pci 1f.6 off end - end - - device pci 00.0 on end # Northbridge - device pci 00.1 on end # Northbridge Error reporting - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge - device pci 00.1 on end # I/O apic - device pci 00.2 on end # bridge - device pci 00.3 on end # I/O apic - end - end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end - end - - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # CPU 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # CPU 1 - device apic 6 on end - end - end -end diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb deleted file mode 100644 index 87be848afb..0000000000 --- a/src/mainboard/supermicro/x6dhe_g/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb deleted file mode 100644 index 11569d9a5b..0000000000 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ /dev/null @@ -1,190 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 # MCH - chip drivers/generic/debug # DEBUGGING - device pnp 00.0 off end - device pnp 00.1 off end - device pnp 00.2 off end - device pnp 00.3 off end - end - device pci_domain 0 on - chip southbridge/intel/i82801er # ICH5R - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1c.0 on - chip drivers/generic/generic - device pci 01.0 on end # onboard gige1 - device pci 02.0 on end # onboard gige2 - end - end - - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.4 on end # Southbridge Watchdog timer - device pci 1d.5 on end # Southbridge I/O apic1 - device pci 1d.7 on end - - # VGA / PCI 32-bit - device pci 1e.0 on - chip drivers/generic/generic - device pci 01.0 on end - end - end - - - device pci 1f.0 on # ISA bridge - chip superio/nsc/pc87427 - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.9 off end - device pnp 2e.a on end - device pnp 2e.b off end - end - end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end # SMBus - device pci 1f.5 off end - device pci 1f.6 off end - end - - device pci 00.0 on end # Northbridge - device pci 00.1 on end # Northbridge Error reporting - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge - device pci 00.1 on end # I/O apic - device pci 00.2 on end # bridge - device pci 00.3 on end # I/O apic - end - end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end - end - - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # CPU 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # CPU 1 - device apic 6 on end - end - end -end diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb deleted file mode 100644 index 87be848afb..0000000000 --- a/src/mainboard/supermicro/x6dhe_g2/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb deleted file mode 100644 index dc2dd1265f..0000000000 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ /dev/null @@ -1,187 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> VGA - device pci 1e.0 on end - - # -> IDE - device pci 1f.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.9 off end - device pnp 2e.a on end - device pnp 2e.b off end - end - end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on end - device pci 03.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 2 - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on - # On board gig e1000 - chip drivers/generic/generic - device pci 02.0 on end - device pci 02.1 on end - end - end - device pci 0.3 on end - end - end - device pci 04.0 on - chip southbridge/intel/pxhd # pxhd2 - # Bus bridges and ioapics usually bus 5 - device pci 0.0 on end - # Slot 6 is usually 6:2.0 - device pci 0.1 on end - device pci 0.2 on end - # Slot 7 is usually 7:2.0 - device pci 0.3 on end - end - end - device pci 06.0 on end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end - end - end - register "intrline" = "0x00070105" -end - diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb deleted file mode 100644 index d8b836bfc4..0000000000 --- a/src/mainboard/supermicro/x6dhr_ig/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb deleted file mode 100644 index 9e8ce1427a..0000000000 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ /dev/null @@ -1,178 +0,0 @@ -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.9 off end - device pnp 2e.a on end - device pnp 2e.b off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device apic 6 on end - end - end - register "intrline" = "0x00070105" -end - diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb deleted file mode 100644 index d8b836bfc4..0000000000 --- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb +++ /dev/null @@ -1,228 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_BTEXT -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY - - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1048576 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## Use timer2 -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_LOGICAL_CPUS=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="X6DHR" -default CONFIG_MAINBOARD_VENDOR= "Supermicro" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -## -## Don't enable the btext console -## -default CONFIG_CONSOLE_BTEXT=0 - - -### End Options.lb -end diff --git a/src/mainboard/technexion/tim5690/Config.lb b/src/mainboard/technexion/tim5690/Config.lb deleted file mode 100644 index 619e76e074..0000000000 --- a/src/mainboard/technexion/tim5690/Config.lb +++ /dev/null @@ -1,261 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -object vgabios.o -object tn_post_code.o -object speaker.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -#The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "1" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "0" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/technexion/tim5690/Options.lb b/src/mainboard/technexion/tim5690/Options.lb deleted file mode 100644 index 774baafb4f..0000000000 --- a/src/mainboard/technexion/tim5690/Options.lb +++ /dev/null @@ -1,303 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_VIDEO_MB -uses CONFIG_GFXUMA -uses CONFIG_HAVE_MAINBOARD_RESOURCES -uses CONFIG_VGA_ROM_RUN - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 - -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 -default CONFIG_VGA_ROM_RUN=1 - -# BTDC: Only one HT device on Herring. -#HT Unit ID offset -#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="tim5690" -default CONFIG_MAINBOARD_VENDOR="technexion" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_VIDEO_MB=1 -default CONFIG_GFXUMA=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -### End Options.lb -end diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb deleted file mode 100644 index fde48a1cc2..0000000000 --- a/src/mainboard/technexion/tim8690/Config.lb +++ /dev/null @@ -1,258 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -#The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/technexion/tim8690/Options.lb b/src/mainboard/technexion/tim8690/Options.lb deleted file mode 100644 index 9589fcd97b..0000000000 --- a/src/mainboard/technexion/tim8690/Options.lb +++ /dev/null @@ -1,300 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_VIDEO_MB -uses CONFIG_GFXUMA -uses CONFIG_HAVE_MAINBOARD_RESOURCES - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 - -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -# BTDC: Only one HT device on Herring. -#HT Unit ID offset -#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="tim8690" -default CONFIG_MAINBOARD_VENDOR="technexion" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_VIDEO_MB=1 -default CONFIG_GFXUMA=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -### End Options.lb -end diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb deleted file mode 100644 index fdc26ea8df..0000000000 --- a/src/mainboard/technologic/ts5300/Config.lb +++ /dev/null @@ -1,111 +0,0 @@ -default CONFIG_ROM_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = 0x10000 - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 32 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - - -# VGA console -#if CONFIG_CONSOLE_VGA -# default CONFIG_PCI_ROM_RUN=1 -#end -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -dir /devices -config chip.h - -chip cpu/amd/sc520 - device pci_domain 0 on - device pci 0.0 on end - -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" - end - -end diff --git a/src/mainboard/technologic/ts5300/Options.lb b/src/mainboard/technologic/ts5300/Options.lb deleted file mode 100644 index 1028c980a0..0000000000 --- a/src/mainboard/technologic/ts5300/Options.lb +++ /dev/null @@ -1,135 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_COMPRESS -uses CONFIG_ROM_PAYLOAD -uses CONFIG_USE_INIT -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS - - -uses CONFIG_CONSOLE_SERIAL8250 - - -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL - -default CONFIG_CONSOLE_SERIAL8250=1 -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x2f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - - -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=2 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" -end diff --git a/src/mainboard/televideo/tc7020/Config.lb b/src/mainboard/televideo/tc7020/Config.lb deleted file mode 100644 index ff76635ce8..0000000000 --- a/src/mainboard/televideo/tc7020/Config.lb +++ /dev/null @@ -1,130 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Kenji Noguchi <tokoy246@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/amd/model_gx1/cpu_setup.inc -mainboardinit cpu/amd/model_gx1/gx_setup.inc -mainboardinit ./auto.inc - -dir /pc80 -config chip.h - -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, Advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe8 - end - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - device pci 14.0 on end # MiniPCI slot - device pci 15.0 on end # Ethernet (onboard) - register "ide0_enable" = "1" - register "ide1_enable" = "0" # Not available/needed on this board - end - end - chip cpu/amd/model_gx1 # CPU - end -end diff --git a/src/mainboard/televideo/tc7020/Options.lb b/src/mainboard/televideo/tc7020/Options.lb deleted file mode 100644 index 9b0cfb833c..0000000000 --- a/src/mainboard/televideo/tc7020/Options.lb +++ /dev/null @@ -1,102 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_VIDEO_MB -uses CONFIG_SPLASH_GRAPHIC -uses CONFIG_GX1_VIDEO -uses CONFIG_GX1_VIDEOMODE -uses CONFIG_PIRQ_ROUTE - -## Enable VGA with a splash screen (only 640x480 to run on most monitors). -## We want to support up to 1024x768@16 so we need 2MiB video memory. -## Note: Higher resolutions might need faster SDRAM speed. -default CONFIG_GX1_VIDEO = 1 -default CONFIG_GX1_VIDEOMODE = 0 -default CONFIG_SPLASH_GRAPHIC = 1 -default CONFIG_VIDEO_MB = 2 - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_MAINBOARD_VENDOR = "TeleVideo" -default CONFIG_MAINBOARD_PART_NUMBER = "TC7020" -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_PIRQ_ROUTE=1 -default CONFIG_IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc " -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 -end diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb deleted file mode 100644 index a509341c07..0000000000 --- a/src/mainboard/thomson/ip1000/Config.lb +++ /dev/null @@ -1,144 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/intel/i82830 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x06" - register "pirqc_routing" = "0x07" - register "pirqd_routing" = "0x09" - register "pirqe_routing" = "0x0a" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1d.0 on end # USB UHCI Controller #1 - device pci 1d.1 on end # USB UHCI Controller #2 - device pci 1d.2 on end # USB UHCI Controller #3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on # PCI bridge - device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet - end - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # Com2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.9 off end # Game port - device pnp 2e.a on # PME - io 0x60 = 0x800 - end - device pnp 2e.b off end # MPU-401 - end - end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem - end - end - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479 - device apic 0 on end # APIC - end - end -end - diff --git a/src/mainboard/thomson/ip1000/Options.lb b/src/mainboard/thomson/ip1000/Options.lb deleted file mode 100644 index 655d94fae7..0000000000 --- a/src/mainboard/thomson/ip1000/Options.lb +++ /dev/null @@ -1,96 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CC -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_VGA -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_IOAPIC -uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE -uses CONFIG_PCI_ROM_RUN -uses CONFIG_ROM_PAYLOAD -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_UDELAY_TSC -uses CONFIG_VIDEO_MB -uses CONFIG_CROSS_COMPILE -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_FALLBACK_SIZE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_HEAP_SIZE -uses HOSTCC -uses CONFIG_IRQ_SLOT_COUNT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_OBJCOPY -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_LCS -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_GENERATE_ACPI_TABLES = 0 -default CONFIG_IOAPIC = 0 -default CONFIG_HAVE_OPTION_TABLE = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 -default CONFIG_VIDEO_MB = 0 -default CONFIG_STACK_SIZE = 0x2000 -default CONFIG_HEAP_SIZE = 0x4000 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_ROM_PAYLOAD = 1 -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAINBOARD_VENDOR = "THOMSON" -default CONFIG_MAINBOARD_PART_NUMBER = "IP1000" -end diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb deleted file mode 100644 index 31e0fb8056..0000000000 --- a/src/mainboard/tyan/s1846/Config.lb +++ /dev/null @@ -1,128 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/nsc/pc87309 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Power management - end - device pnp 2e.5 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - end - end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb deleted file mode 100644 index 975a085b1a..0000000000 --- a/src/mainboard/tyan/s1846/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -end diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb deleted file mode 100644 index 4f9fc5b20b..0000000000 --- a/src/mainboard/tyan/s2735/Config.lb +++ /dev/null @@ -1,179 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/x86/car/cache_as_ram.lds - end - - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/x86/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2735 -chip northbridge/intel/e7501 - device pci_domain 0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 2.0 on - chip southbridge/intel/i82870 - device pci 1c.0 on end - device pci 1d.0 on - device pci 1.0 on end # intel lan - device pci 1.1 on end - end - device pci 1e.0 on end - device pci 1f.0 on end - end - end - device pci 6.0 on end - chip southbridge/intel/i82801er - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - device pci 1e.0 on - device pci 1.0 on end # intel lan 10/100 - device pci 2.0 on end # ati - end - device pci 1f.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1f.1 off end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - end # SB - end # PCI_DOMAIN - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 - device apic 6 on end - end - end -end - diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb deleted file mode 100644 index 61933d2233..0000000000 --- a/src/mainboard/tyan/s2735/Options.lb +++ /dev/null @@ -1,256 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_INIT -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_SERIAL_CPU_INIT -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -#512K bytes -default CONFIG_ROM_SIZE=524288 - -#1M bytes -#default CONFIG_ROM_SIZE=1048576 - - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -#default CONFIG_CONSOLE_VGA=1 -#default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -#default CONFIG_DCACHE_RAM_BASE=0xF2000000 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_PRINTK_IN_CAR=1 - - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2735" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb deleted file mode 100644 index eaa338e041..0000000000 --- a/src/mainboard/tyan/s2850/Config.lb +++ /dev/null @@ -1,197 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2850 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # LDT0 - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - #chip drivers/ati/ragexl - device pci b.0 on end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device pci 1.5 on end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end - diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb deleted file mode 100644 index a53d5b7272..0000000000 --- a/src/mainboard/tyan/s2850/Options.lb +++ /dev/null @@ -1,244 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=12 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="S2850" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb deleted file mode 100644 index 6145ba7428..0000000000 --- a/src/mainboard/tyan/s2875/Config.lb +++ /dev/null @@ -1,189 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2875 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci 5.0 on end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 on end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end - diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb deleted file mode 100644 index 51913e30fb..0000000000 --- a/src/mainboard/tyan/s2875/Options.lb +++ /dev/null @@ -1,245 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=13 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2875" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb deleted file mode 100644 index 5e72afbbfb..0000000000 --- a/src/mainboard/tyan/s2880/Config.lb +++ /dev/null @@ -1,200 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2880 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on - device pci 9.0 on end #broadcom - device pci 9.1 on end -# chip drivers/lsi/53c1030 -# device pci a.0 on end -# device pci a.1 on end -# register "fw_address" = "0xfff8c000" -# end - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci 5.0 on end #some sata - device pci 6.0 on end #adti - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end - diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb deleted file mode 100644 index c41e03f356..0000000000 --- a/src/mainboard/tyan/s2880/Options.lb +++ /dev/null @@ -1,244 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=13 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=0 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="S2880" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb deleted file mode 100644 index a46e0ef661..0000000000 --- a/src/mainboard/tyan/s2881/Config.lb +++ /dev/null @@ -1,233 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 -object get_bus_conf.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2881 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - device pci a.0 on end # Adaptic - device pci a.1 on end - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci 5.0 on end # SiI - device pci 6.0 on end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3 - device i2c 2d on end - end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN - device i2c 2a on end - end - chip drivers/generic/generic # Winbond HWM 0x92 - device i2c 49 on end - end - chip drivers/generic/generic # Winbond HWM 0x94 - device i2c 4a on end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end - diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb deleted file mode 100644 index 59002d27de..0000000000 --- a/src/mainboard/tyan/s2881/Options.lb +++ /dev/null @@ -1,261 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0a - -##real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2881" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb deleted file mode 100644 index 266733154e..0000000000 --- a/src/mainboard/tyan/s2882/Config.lb +++ /dev/null @@ -1,227 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2882 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on - device pci 6.0 on end # adaptec - device pci 6.1 on end - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci 5.0 on end - # chip drivers/ati/ragexl - device pci 6.0 on end - # end - device pci 8.0 on end #intel 10/100 - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.3 on -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 54 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 55 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 56 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 57 on end -# end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # NB - end #pci_domain -end - diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb deleted file mode 100644 index d4ff6fef88..0000000000 --- a/src/mainboard/tyan/s2882/Options.lb +++ /dev/null @@ -1,244 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="S2882" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb deleted file mode 100644 index 26389a18ce..0000000000 --- a/src/mainboard/tyan/s2885/Config.lb +++ /dev/null @@ -1,233 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 -object get_bus_conf.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s2885 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # LDT0 - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - end - device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on - device pci 9.0 on end # broadcom 5703 - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci b.0 on end # SiI 3114 - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # acpi - device pci 1.5 on end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - - end #pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end -# device pnp 0.4 off end -# device pnp 0.5 on end -# end -end - diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb deleted file mode 100644 index fc43fc834d..0000000000 --- a/src/mainboard/tyan/s2885/Options.lb +++ /dev/null @@ -1,269 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0a - -##real SB Unit ID, default is 0x20, mean dont touch it at last -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2885" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb deleted file mode 100644 index 42627a35f1..0000000000 --- a/src/mainboard/tyan/s2891/Config.lb +++ /dev/null @@ -1,123 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/ati/ragexl - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb -end - -if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end -else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for CK804 -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -include devicetree.cb diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb deleted file mode 100644 index a0ed35b74c..0000000000 --- a/src/mainboard/tyan/s2891/Options.lb +++ /dev/null @@ -1,302 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_LOW_TABLES -uses CONFIG_MULTIBOOT -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_ID_SECTION_OFFSET - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE=512*1024 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_LOW_TABLES=1 -default CONFIG_MULTIBOOT=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_VGA_ROM_RUN=1 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - - -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2891" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb deleted file mode 100644 index 38645588c7..0000000000 --- a/src/mainboard/tyan/s2892/Config.lb +++ /dev/null @@ -1,124 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/ati/ragexl - -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb -end - -if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end -else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for CK804 -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -include devicetree.cb diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb deleted file mode 100644 index e3f1606cf3..0000000000 --- a/src/mainboard/tyan/s2892/Options.lb +++ /dev/null @@ -1,290 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_LOW_TABLES -uses CONFIG_MULTIBOOT -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_ID_SECTION_OFFSET - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE=1024*1024 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_LOW_TABLES=1 -default CONFIG_MULTIBOOT=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_VGA_ROM_RUN=1 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2892" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb deleted file mode 100644 index 1b7f808b40..0000000000 --- a/src/mainboard/tyan/s2895/Config.lb +++ /dev/null @@ -1,145 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.dsl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o - #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb -end - -if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end -else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for CK804 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -end - -## -## Setup Cache-As-Ram -## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -include devicetree.cb diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb deleted file mode 100644 index 6659c9ad38..0000000000 --- a/src/mainboard/tyan/s2895/Options.lb +++ /dev/null @@ -1,311 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_LOW_TABLES -uses CONFIG_MULTIBOOT -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_RAMTOP - -uses CONFIG_ID_SECTION_OFFSET - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE=1024*1024 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_LOW_TABLES=1 -default CONFIG_MULTIBOOT=0 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 -default CONFIG_VGA_ROM_RUN=1 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -default CONFIG_SERIAL_CPU_INIT=0 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="s2895" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb deleted file mode 100644 index 35511f83ca..0000000000 --- a/src/mainboard/tyan/s2912/Config.lb +++ /dev/null @@ -1,315 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb deleted file mode 100644 index 52d8202437..0000000000 --- a/src/mainboard/tyan/s2912/Options.lb +++ /dev/null @@ -1,355 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC -uses CONFIG_K8_HT_FREQ_1G_SUPPORT - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 -#default CONFIG_ROM_SIZE=0x100000 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=2048*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 -## extra SSDT num -default CONFIG_ACPI_SSDTX_NUM=3 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 - -#default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=0 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#default CONFIG_USBDEBUG_DIRECT=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x08000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default CONFIG_MEM_TRAIN_SEQ=1 -default CONFIG_WAIT_BEFORE_CPUS_INIT=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="S2912" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb deleted file mode 100644 index 538ababb8f..0000000000 --- a/src/mainboard/tyan/s2912_fam10/Config.lb +++ /dev/null @@ -1,320 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/failovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## ROMSTRAP table for MCP55 -## -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/mcp55/romstrap.inc - ldscript /southbridge/nvidia/mcp55/romstrap.lds - end -end - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -dir /southbridge/nvidia/mcp55 - -chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_F_1207 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # SB on link 2.0. - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on - device pci 4.0 on end - end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb deleted file mode 100644 index d9444d810a..0000000000 --- a/src/mainboard/tyan/s2912_fam10/Options.lb +++ /dev/null @@ -1,362 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_ACPI_SSDTX_NUM -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC - -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SERIAL_CPU_INIT - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_RAMTOP - -uses CONFIG_PCI_BUS_SEGN_BITS - -uses CONFIG_AP_CODE_IN_CAR - -uses CONFIG_MEM_TRAIN_SEQ - -uses CONFIG_WAIT_BEFORE_CPUS_INIT - -uses CONFIG_AMDMCT - -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_AMD_UCODE_PATCH_FILE -uses CONFIG_ID_SECTION_OFFSET - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 -#default CONFIG_ROM_SIZE=0x100000 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## - -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_RAMTOP=16384*1024 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=0 -## extra SSDT num -default CONFIG_ACPI_SSDTX_NUM=31 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS -default CONFIG_LOGICAL_CPUS=1 - -#default CONFIG_SERIAL_CPU_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x00 -default CONFIG_LIFT_BSP_APIC_ID=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 -#1G -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#default CONFIG_USBDEBUG_DIRECT=1 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default CONFIG_HT_CHAIN_UNITID_BASE=1 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc4000 -default CONFIG_DCACHE_RAM_SIZE=0x0c000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 -default CONFIG_USE_INIT=0 - -default CONFIG_MEM_TRAIN_SEQ=2 -default CONFIG_WAIT_BEFORE_CPUS_INIT=0 -default CONFIG_AMDMCT = 1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="S2912 (Fam10)" -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912 - -## -## Set microcode patch file name -## -## Barcelona rev DR-Ax: "mc_patch_01000020.h" -## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h" -## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" -## Shanghai rev DA-C2: "mc_patch_0100009f.h" -## -default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0xc0000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00200000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_ID_SECTION_OFFSET=0x80 - -### End Options.lb -end diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb deleted file mode 100644 index 5e1aaf5130..0000000000 --- a/src/mainboard/tyan/s4880/Config.lb +++ /dev/null @@ -1,195 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s4880 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on -# chip drivers/lsi/53c1030 -# device pci 4.0 on end -# device pci 4.1 on end -# register "fw_address" = "0xfff8c000" -# end - device pci 9.0 on end - device pci 9.1 on end - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci 6.0 on end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on end - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - - end #pci_domain -end - diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb deleted file mode 100644 index 05490b785f..0000000000 --- a/src/mainboard/tyan/s4880/Options.lb +++ /dev/null @@ -1,253 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=22 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=8 -default CONFIG_MAX_PHYSICAL_CPUS=4 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PART_NUMBER="s4880" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb deleted file mode 100644 index bbb94f2116..0000000000 --- a/src/mainboard/tyan/s4882/Config.lb +++ /dev/null @@ -1,302 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -# sample config for tyan/s4882 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT0 - device pci 18.0 on # northbridge - # devices on link 1, link 1 == LDT 1 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on -# chip drivers/lsi/53c1030 -# device pci 4.0 on end -# device pci 4.1 on end -# register "fw_address" = "0xfff8c000" -# end - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - #chip drivers/ati/ragexl - device pci 6.0 on end - #end - device pci 5.0 on end #SiI - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on -# chip drivers/i2c/i2cmux # pca9556 smbus mux -# device i2c 18 on #0 pca9516 2, 1 -# chip drivers/i2c/lm63 #cpu0 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #1 pca9516 1, 1 -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #2 pca9516 1, 2 -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #3 pca9516 1, 3 -# chip drivers/generic/generic #dimm 3-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 3-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 3-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 3-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #4 pca9516 1, 4 -# chip drivers/generic/generic #dimm 2-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 2-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 2-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 2-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #5 pca9516 2, 2 -# chip drivers/i2c/lm63 #cpu1 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #6 pca9516 2, 3 -# chip drivers/i2c/lm63 #cpu2 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #7 pca9516 2, 4 -# chip drivers/i2c/lm63 #cpu3 temp -# device i2c 4c on end -# end -# end -# end # i2cmux -# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... -# device i2c 2e on end -# end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid -# device i2c 2a on end -# end -# chip drivers/generic/generic # Winbond HWM 0x92 -# device i2c 49 on end -# end -# chip drivers/generic/generic # Winbond HWM 0x94 -# device i2c 4a on end -# end -# chip drivers/generic/generic # ?? -# device i2c 69 on end -# end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - - end -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 on end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 on end # dual core msr -# device pnp 0.6 on end # cache size -# device pnp 0.7 on end # tsc -# end -end - diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb deleted file mode 100644 index 820fc3be2f..0000000000 --- a/src/mainboard/tyan/s4882/Options.lb +++ /dev/null @@ -1,252 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=22 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=8 -default CONFIG_MAX_PHYSICAL_CPUS=4 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -#default CONFIG_CONSOLE_VGA=1 -#default CONFIG_PCI_ROM_RUN=1 - - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xcf000 -default CONFIG_DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 - -default CONFIG_ENABLE_APIC_EXT_ID=1 -default CONFIG_APIC_ID_OFFSET=0x10 -default CONFIG_LIFT_BSP_APIC_ID=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_VENDOR="Tyan" -default CONFIG_MAINBOARD_PART_NUMBER="s4882" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00002000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb deleted file mode 100644 index 42d62cbacf..0000000000 --- a/src/mainboard/via/epia-cn/Config.lb +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - device pci f.0 on end # IDE - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI - device pci 11.0 on # Southbridge LPC - chip superio/via/vt1211 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end - device apic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC - end - end -end diff --git a/src/mainboard/via/epia-cn/Options.lb b/src/mainboard/via/epia-cn/Options.lb deleted file mode 100644 index 718c75d8fb..0000000000 --- a/src/mainboard/via/epia-cn/Options.lb +++ /dev/null @@ -1,98 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_TTYS0_BAUD -uses CONFIG_VIDEO_MB -uses CONFIG_IOAPIC -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_IOAPIC = 1 -default CONFIG_VIDEO_MB = 32 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 9 -default CONFIG_GENERATE_ACPI_TABLES = 0 -default CONFIG_HAVE_OPTION_TABLE = 1 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_USE_FALLBACK_IMAGE = 1 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" - -end diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb deleted file mode 100644 index 011ce5ad24..0000000000 --- a/src/mainboard/via/epia-m/Config.lb +++ /dev/null @@ -1,159 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -object vgabios.o - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/via/vt8623 - - device apic_cluster 0 on - chip cpu/via/model_c3 - device apic 0 on end - end - end - - device pci_domain 0 on - chip southbridge/via/vt8235 - - device pci 10.0 on end # USB 1.1 - device pci 10.1 on end # USB 1.1 - device pci 10.2 on end # USB 1.1 - device pci 10.3 on end # USB 2 - - device pci 11.0 on # Southbridge - chip superio/via/vt1211 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - - end - end - - device pci 11.1 on end # IDE - # 2-4 non existant? - device pci 11.5 on end # AC97 Audio - device pci 11.6 off end # AC97 Modem - device pci 12.0 on end # Ethernet - end -# This is on the EPIA MII, not the M. - chip southbridge/ricoh/rl5c476 - register "enable_cf" = "1" - device pci 0a.0 on end - device pci 0a.1 on end - end - end -end diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb deleted file mode 100644 index 4583331f55..0000000000 --- a/src/mainboard/via/epia-m/Options.lb +++ /dev/null @@ -1,135 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_TTYS0_BAUD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_CONSOLE_VGA=0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Use TSC for udelay. -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=5 - - -## -## Build code to load acpi tables -## -default CONFIG_GENERATE_ACPI_TABLES=1 - - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -default CONFIG_CONSOLE_SERIAL8250=1 -end diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb deleted file mode 100644 index d7d7cbedc8..0000000000 --- a/src/mainboard/via/epia-m700/Config.lb +++ /dev/null @@ -1,165 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 One Laptop per Child, Association, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -driver wakeup.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - # object ssdt.o - object acpi_tables.o -end -# These lines maybe noused. -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -if CONFIG_USE_DCACHE_RAM - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" - action "perl -e 's/.rodata/.rom.data/g' -pi $@" - action "perl -e 's/.text/.section .rom.text/g' -pi $@" - end - end -end -mainboardinit cpu/x86/16bit/entry16.inc -ldscript /cpu/x86/16bit/entry16.lds - -mainboardinit northbridge/via/vx800/romstrap.inc -ldscript /northbridge/via/vx800/romstrap.lds - -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -# mainboardinit arch/i386/lib/cpu_reset.inc -# Here cpu_reset.inc have label _cpu_reset, which is needed in failover.c, -# but cpu_reset.inc also has code to jump to __main() which is not included -# in cache_as_ram_auto_auto.c. - -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -if CONFIG_USE_DCACHE_RAM - mainboardinit cpu/via/car/cache_as_ram.inc -end - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - # failover.inc need definition in cpu_reset.inc, but we do not include - # cpu_reset.inc,so ... - # mainboardinit ./failover.inc -end -# mainboardinit cpu/x86/fpu_enable.inc - -if CONFIG_USE_DCACHE_RAM - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end -end - -# mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 - -config chip.h - -chip northbridge/via/vx800 # Northbridge - device pci_domain 0 on - device pci 0.0 on end # Host Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # PCI to PCI Bridge - device pci 0.4 on end # Power Management - device pci 0.5 on end # APIC and Central Traffic Control - device pci 0.6 on end # Scratch Registers - device pci 0.7 on end # North-South Module Interface Control - device pci 1.0 on end # PCI Bridge - device pci f.0 on end # IDE/SATA - # device pci f.1 on end # IDE - device pci 10.0 on end # USB 1.1 - device pci 10.1 on end # USB 1.1 - device pci 10.2 on end # USB 1.1 - device pci 10.4 on end # USB 2.0 - device pci 11.0 on # Bus Control and Power Management (SB, LPC) - chip superio/winbond/w83697hf - # TODO: Check all devices, this may need some more work. - device pnp 2e.0 off # Floppy (N/A?) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port (N/A?) - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, GPIO 1 - device pnp 2e.8 off end # MIDI port, GPIO 5 - device pnp 2e.9 off end # GPIO 2-4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM - io 0x60 = 0x290 - end - end - end - device pci 11.7 on end # North-South Module Interface Control - device pci 14.0 on end # HD Audio (Azalia) - end - device apic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC - end - end -end diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb deleted file mode 100644 index fffa5502d7..0000000000 --- a/src/mainboard/via/epia-m700/Options.lb +++ /dev/null @@ -1,138 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 One Laptop per Child, Association, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_TTYS0_BAUD -uses CONFIG_VIDEO_MB -uses CONFIG_IOAPIC - -## New options -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -#uses MAX_RAM_SLOTS -#uses USB_ENABLE -#uses EHCI_ENABLE -#uses HPET_ENABLE -#uses USB_PORTNUM -#uses FULL_ROM_SIZE -#uses FULL_ROM_BASE -#uses PAYLOAD_IS_SEABIOS -#uses VIACONFIG_TOP_SM_SIZE_MB -#uses VIACONFIG_VGA_PCI_10 -#uses VIACONFIG_VGA_PCI_14 - -## New options -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xffef0000 -# default CONFIG_DCACHE_RAM_BASE = 0xffbf0000 -# default CONFIG_DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. -default CONFIG_DCACHE_RAM_SIZE = 8 * 1024 -default CONFIG_USE_INIT = 0 -#default MAX_RAM_SLOTS = 2 -#default USB_ENABLE = 1 -#default EHCI_ENABLE = 1 -#default HPET_ENABLE = 1 -#default USB_PORTNUM = 2 -#default FULL_ROM_SIZE = 512 * 1024 -#default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1) -#default VIACONFIG_TOP_SM_SIZE_MB = 0 -# default VIACONFIG_VGA_PCI_10 = 0xd0000008 -# default VIACONFIG_VGA_PCI_14 = 0xfd000000 -#default VIACONFIG_VGA_PCI_10 = 0xf8000008 -#default VIACONFIG_VGA_PCI_14 = 0xfc000000 - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_IOAPIC = 1 - -# Define framebuffer size of VX800's integrated graphics card. -# Supports: 32, 64, 128, 256. -default CONFIG_VIDEO_MB = 64 - -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_HARD_RESET = 0 -# TODO: There is an irq_tables.c file, should it be used? -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_IRQ_SLOT_COUNT = 13 -default CONFIG_GENERATE_ACPI_TABLES = 1 -default CONFIG_HAVE_OPTION_TABLE = 1 -default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_USE_FALLBACK_IMAGE = 1 -default CONFIG_STACK_SIZE = 16 * 1024 -default CONFIG_HEAP_SIZE = 20 * 1024 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 - -end diff --git a/src/mainboard/via/epia-n/Config.lb b/src/mainboard/via/epia-n/Config.lb deleted file mode 100644 index ac0ef8bde9..0000000000 --- a/src/mainboard/via/epia-n/Config.lb +++ /dev/null @@ -1,202 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 - -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -#object vgabios.o - -if CONFIG_GENERATE_MP_TABLE object mptable.o end - -if CONFIG_GENERATE_ACPI_TABLES -#acpi_create_fadt is located in VT8237R code - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/via/cn400 # Northbridge - - device apic_cluster 0 on # APIC cluster - chip cpu/via/model_c3 # VIA C3 - device apic 0 on end # APIC - end - end - - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - device pci f.0 on end # IDE/SATA - device pci f.1 on end # IDE - register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97 - register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 10.5 off end # USB Direct - device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off # IR Port - io 0x60 = 0x000 - end - device pnp 2e.7 off # GPIO 1 - io 0x60 = 0x201 # 0x201 - end - device pnp 2e.8 off # GPIO 5 - io 0x60 = 0x330 # 0x330 - end - device pnp 2e.9 off # GPIO 2, 3,and 4 - io 0x60 = 0x000 # - end - device pnp 2e.a off # ACPI - io 0x60 = 0x000 # - end - device pnp 2e.b on # HWM - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 11.5 off end # AC'97 audio - device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end -end diff --git a/src/mainboard/via/epia-n/Options.lb b/src/mainboard/via/epia-n/Options.lb deleted file mode 100644 index 416b8128d9..0000000000 --- a/src/mainboard/via/epia-n/Options.lb +++ /dev/null @@ -1,113 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_RAMTOP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_SMP -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_TTYS0_BAUD -uses CONFIG_VIDEO_MB -uses CONFIG_IOAPIC -uses CONFIG_COMPRESS -uses CONFIG_EPIA_VT8237R_INIT -uses CONFIG_HAVE_MAINBOARD_RESOURCES -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -default CONFIG_EPIA_VT8237R_INIT = 1 -#default CONFIG_RAMTOP = 4 * 1024*1024 -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_COMPRESS = 1 -default CONFIG_IOAPIC = 1 -default CONFIG_VIDEO_MB = 64 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_HAVE_FAILOVER_BOOT = 0 -default CONFIG_USE_FAILOVER_IMAGE = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_SMP = 1 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_GENERATE_ACPI_TABLES = 1 -default CONFIG_HAVE_OPTION_TABLE = 1 -#default CONFIG_ROM_IMAGE_SIZE = 67 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_USE_FALLBACK_IMAGE = 1 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" -#default CONFIG_MAINBOARD = "EPIA-N" -default CONFIG_HAVE_MAINBOARD_RESOURCES = 1 - -end diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb deleted file mode 100644 index c75c21e060..0000000000 --- a/src/mainboard/via/epia/Config.lb +++ /dev/null @@ -1,156 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/via/vt8601 - device pci_domain 0 on - device pci 0.0 on end # Northbridge -# device pci 0.1 on # AGP bridge - # device pci 0.0 on end # Integrated VGA -# end - chip southbridge/via/vt8231 - register "enable_native_ide" = "0" - register "enable_com_ports" = "1" - register "enable_keyboard" = "0" - device pci 11.0 on # Southbrdge - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - register "com1" = "{CONFIG_TTYS0_BAUD}" - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - end - device pci 11.1 on end # Ide - device pci 11.2 off end # Usb port 0-1 - device pci 11.3 off end # Usb port 2-3 - device pci 11.4 off end # ACPI - device pci 11.5 off end # AC97 Audio - device pci 11.6 on end # AC97 Modem - device pci 12.0 on end # Ethernet - end - end - - device apic_cluster 0 on - chip cpu/via/model_c3 - device apic 0 on end - end - end -end diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb deleted file mode 100644 index 466ffcc382..0000000000 --- a/src/mainboard/via/epia/Options.lb +++ /dev/null @@ -1,143 +0,0 @@ -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_UDELAY_IO -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY - -# logging -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL - -# logging -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL - -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 - -default CONFIG_CONSOLE_SERIAL8250=1 -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE=0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=0 - -## -## use io based udelay function -## disable IO and enable TSC on Nehemiah boards -## -default CONFIG_UDELAY_IO=1 -default CONFIG_UDELAY_TSC=0 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=5 -#object irq_tables.o - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" -end diff --git a/src/mainboard/via/pc2500e/Config.lb b/src/mainboard/via/pc2500e/Config.lb deleted file mode 100644 index 01c226670e..0000000000 --- a/src/mainboard/via/pc2500e/Config.lb +++ /dev/null @@ -1,161 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object dsdt.o - object acpi_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc -dir /pc80 -config chip.h - -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - device pci f.0 on end # SATA - device pci f.1 on end # IDE - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI - device pci 11.0 on # Southbridge LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # COM2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 9 - end - device pnp 2e.5 off # PS/2 keyboard (not used) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # PS/2 mouse (not used) - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x0000 - io 0x62 = 0x0800 - io 0x64 = 0x0000 - end - device pnp 2e.8 off # MIDI port (N/A) - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # Game port (N/A) - io 0x60 = 0x201 - end - device pnp 2e.a on # Consumer IR - io 0x60 = 0x310 - irq 0x70 = 11 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 modem (N/A) - device pci 12.0 on end # Ethernet - end - end - device apic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device apic 0 on end # APIC - end - end -end diff --git a/src/mainboard/via/pc2500e/Options.lb b/src/mainboard/via/pc2500e/Options.lb deleted file mode 100644 index 9e4896050b..0000000000 --- a/src/mainboard/via/pc2500e/Options.lb +++ /dev/null @@ -1,109 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_SMP -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_VIDEO_MB -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_IOAPIC = 1 -default CONFIG_VIDEO_MB = 32 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_SMP = 1 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 10 -default CONFIG_GENERATE_ACPI_TABLES = 0 -default CONFIG_HAVE_OPTION_TABLE = 1 -default CONFIG_USE_FALLBACK_IMAGE = 1 -default CONFIG_MAINBOARD_VENDOR = "VIA" -default CONFIG_MAINBOARD_PART_NUMBER = "pc2500e" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 1 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -end diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb deleted file mode 100644 index 6faa33c3b2..0000000000 --- a/src/mainboard/via/vt8454c/Config.lb +++ /dev/null @@ -1,163 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_MP_TABLE - object mptable.o -end - -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.dsl" - action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -## -## Romcc output -## -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -mainboardinit cpu/via/car/cache_as_ram.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/via/cx700 - device apic_cluster 0 on - chip cpu/via/model_c7 - device apic 0 on end - end - end - device pci_domain 0 on - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on # PCI Bridge - device pci 0.0 on end # Onboard Video - end # PCI Bridge - device pci f.0 on end # IDE/SATA - #device pci f.1 on end # IDE - device pci 10.0 on end # USB 1.1 - device pci 10.1 on end # USB 1.1 - device pci 10.2 on end # USB 1.1 - device pci 10.4 on end # USB 2.0 - device pci 11.0 on # Southbridge LPC - chip superio/via/vt1211 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end # superio - end # pci 11.0 - # 1-4 non existant - #device pci 11.5 on end # AC97 Audio - #device pci 11.6 off end # AC97 Modem - #device pci 12.0 on end # Ethernet - end # pci domain 0 -end # cx700 - diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb deleted file mode 100644 index cb796caf97..0000000000 --- a/src/mainboard/via/vt8454c/Options.lb +++ /dev/null @@ -1,233 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_HAVE_LOW_TABLES - -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET - -uses CONFIG_COMPRESS -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA - -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE - -# compiler specifics -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY - -# Console specifics -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS - -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_PCI_ROM_RUN -uses CONFIG_CONSOLE_VGA -uses CONFIG_SMP -uses CONFIG_IOAPIC - -uses CONFIG_GDB_STUB - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 256*1024 - -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xffef0000 -#default CONFIG_DCACHE_RAM_BASE=0xffbf0000 -#default CONFIG_DCACHE_RAM_BASE=0xfec00000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -### -### Leave this to 0; VGA is handled by seperate code. -### -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_CONSOLE_VGA=0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Use TSC for udelay. -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=15 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to load acpi tables -## -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Build code to fill in tables both in low and high memory -## -default CONFIG_HAVE_LOW_TABLES=1 - - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_SMP=1 -default CONFIG_IOAPIC=1 - -### -### LinuxBIOS layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -## Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 -end - |