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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-29 06:37:52 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-30 05:59:41 +0000
commitaeb85d53e90728bf758b08895c7ed5dbf9cf3062 (patch)
tree175923e7e2483ed3678e7fadf5a7939450cf8c04 /src/mainboard
parent34ac1ab4a3172fc821e47824f107873da25d8991 (diff)
downloadcoreboot-aeb85d53e90728bf758b08895c7ed5dbf9cf3062.tar.xz
binaryPI: Clean leftover romstage prototype
Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/bettong/romstage.c3
-rw-r--r--src/mainboard/amd/db-ft3b-lc/romstage.c6
-rw-r--r--src/mainboard/amd/lamar/romstage.c3
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c3
-rw-r--r--src/mainboard/bap/ode_e21XX/romstage.c3
-rw-r--r--src/mainboard/pcengines/apu2/romstage.c1
6 files changed, 7 insertions, 12 deletions
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 32f52de707..03e6585b9a 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -19,11 +19,10 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
{
u32 val;
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 495ce59eff..2979cf4ae4 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -19,13 +19,13 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{ u32 val;
+static void romstage_main_template(void)
+{
+ u32 val;
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 77a0ea02f7..67485f4f11 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -19,7 +19,6 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/common/amd_defs.h>
@@ -28,7 +27,7 @@
#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
{
u32 val;
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6df12e31cc..519825827a 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -19,12 +19,11 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
{
u32 val;
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index 774cd990b6..4c5a51b5a5 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -19,7 +19,6 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,7 +27,7 @@
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
{
u32 val;
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 4df1e47d99..8eb18181b5 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -21,7 +21,6 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>