diff options
| author | David Hendricks <dhendrix@chromium.org> | 2014-09-29 13:48:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-04 04:03:18 +0200 |
| commit | b4ff291cf6999651cd29b3df671049feffeb5e48 (patch) | |
| tree | 84a7aa6ce4241645757982996a3b4b99ad8c0458 /src/mainboard | |
| parent | f4305468d7c49698548babb7366a3b3d813771d2 (diff) | |
| download | coreboot-b4ff291cf6999651cd29b3df671049feffeb5e48.tar.xz | |
rk3288: Pass SPI bus speed in as parameter to init function
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Original-Reviewed-on: https://chromium-review.googlesource.com/220411
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c
Reviewed-on: http://review.coreboot.org/9245
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/veyron_pinky/bootblock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 5e22d6e7d6..d4f82decff 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); setup_chromeos_gpios(); } |