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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-28 02:09:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-31 06:43:05 +0000 |
| commit | bbed4d9ff0adf1914cf0af15dd430a7c91f638bd (patch) | |
| tree | cbe4ea199d428eb58428afffccf68876fb4a1b98 /src/mainboard | |
| parent | d555d6a88cf733f9f5a0a24694691a6901a81c73 (diff) | |
| download | coreboot-bbed4d9ff0adf1914cf0af15dd430a7c91f638bd.tar.xz | |
mb/amd/mandolin: move PCIe GPP clock setting to devicetree
Checked with the schematics that all PCIe clocks have a corresponding
clock enable pin.
BUG=b:149970243
BRANCH=zork
Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 0004ecd266..c6031302cc 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -115,6 +115,15 @@ chip soc/amd/picasso .flash_ch_en = 0, }" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_REQ" + register "gpp_clk_config[6]" = "GPP_CLK_REQ" + device cpu_cluster 0 on device lapic 0 on end end |