diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-01-13 17:27:36 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-01-16 04:47:13 +0100 |
| commit | d093e4a387d5b15502955841bfc1f44d33059eba (patch) | |
| tree | 16fe4492b2c0be27d5c22c6d6810a36612ab62d8 /src/mainboard | |
| parent | b4a159706ec45c1f8e06b694c3531f94231097d6 (diff) | |
| download | coreboot-d093e4a387d5b15502955841bfc1f44d33059eba.tar.xz | |
mainboard/google/poppy: SD card changes
1. Disable WP
2. Pass SD card detect info in ACPI
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Verified that OS is able to detect SD card and read/write to it.
Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18138
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/poppy/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/gpio.h | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 8699bc1e2c..a9e0cef1b1 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -185,6 +185,9 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_pl2_override" = "7" + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_G7" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index 914b8ed02b..0a2544c0af 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -210,7 +210,7 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), |