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authorAaron Durbin <adurbin@chromium.org>2017-04-16 22:05:36 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-25 18:14:38 +0200
commite4d7abc0d448c7e805f2b48ed1251708d1f84c67 (patch)
tree4ca1014c9d972063e7b44c8a373072008c6015fa /src/mainboard
parent4003950881af6fc4761aa0b177a3670d04ee9881 (diff)
downloadcoreboot-e4d7abc0d448c7e805f2b48ed1251708d1f84c67.tar.xz
lib: provide clearer devicetree semantics
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/bettong/BiosCallOuts.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index 0fe8bd5ec7..e5eed05679 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -109,8 +109,8 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
int spdAddress;
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
- ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
UINT8 spdAddrLookup_rev_F [2][2][4]= {
{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
{ {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */