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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-19 17:39:05 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-21 15:57:16 +0200 |
| commit | ede69f0d627bb7546bff4e6b640e86b641d2ca15 (patch) | |
| tree | accaf70964846c0cea025a44f8cbfd4a1a9fdf37 /src/mainboard | |
| parent | 150f476c966eb09eeb2c4c57769415f7cc15b768 (diff) | |
| download | coreboot-ede69f0d627bb7546bff4e6b640e86b641d2ca15.tar.xz | |
mainboard/google/reef: reverse the memory config bits
I mistakenly assumed the order of the bits matched how one
would assign values as they wrote them msb .. lsb. However, the
gpio lib doesn't do that. Correct the order so that values are
read out correctly.
BUG=chrome-os-partner:54949t
Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15753
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/reef/romstage.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 2c68b60d46..8b7c7a3f58 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -112,7 +112,10 @@ static const struct lpddr4_cfg lp4cfg = { void mainboard_memory_init_params(struct FSPM_UPD *memupd) { int mem_sku; - gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 }; + gpio_t pads[] = { + [3] = MEM_CONFIG3, [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, [0] = MEM_CONFIG0, + }; /* * Read memory SKU id with internal pullups enabled to handle |