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authorNick Vaccaro <nvaccaro@google.com>2020-03-05 18:25:10 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-09 21:26:32 +0000
commitfa0bdd9ee0210b91907b0bbd397583d643dbb887 (patch)
tree5d3b34f35c591d24e0561c6fa34a4b841446b15c /src/mainboard
parent83565dea8638841e522b64e74a4240002bba789d (diff)
downloadcoreboot-fa0bdd9ee0210b91907b0bbd397583d643dbb887.tar.xz
mb/google/volteer: change two gpio settings
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment BUG=b:144933687, b:148179954 BRANCH=none TEST=none Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/gpio.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c
index 3f1f2b0e0f..f6dbed0bee 100644
--- a/src/mainboard/google/volteer/variants/baseboard/gpio.c
+++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c
@@ -29,7 +29,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_A9, NONE, DEEP),
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
PAD_CFG_GPO(GPP_A10, 1, DEEP),
- /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */
+ /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A11, 1, DEEP),
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
@@ -146,7 +146,8 @@ static const struct pad_config gpio_table[] = {
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* C20 : UART2_RXD ==> FPMCU_INT_L */
- PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE),
+ /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */
+ PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
@@ -381,7 +382,7 @@ static const struct pad_config gpio_table[] = {
/* GPD1: ACPRESENT ==> PCH_ACPRESENT */
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
- PAD_CFG_GPI(GPD2, NONE, DEEP),
+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
/* GPD4: SLP_S3# ==> SLP_S3_L */