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| author | Marshall Buschman <mbuschman@lucidmachines.com> | 2011-06-04 15:44:54 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2011-06-04 15:44:54 +0000 |
| commit | fd460e620e8ea945548121d860e032cca9d452bf (patch) | |
| tree | 726f718546d2fd2a3faadf899f49840a619dc450 /src/mainboard | |
| parent | b3ee0d6bd6df18b61779f64c8b0abf19b1dce018 (diff) | |
| download | coreboot-fd460e620e8ea945548121d860e032cca9d452bf.tar.xz | |
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index d761d73555..7f0b9df278 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,6 +47,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { |