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authorElyes HAOUAS <ehaouas@noos.fr>2019-12-08 11:34:24 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-12-10 11:16:07 +0000
commit13746076e95a611b56dfe37519685ae125172bb4 (patch)
tree3d41161b459454cfc89db62c9412e07f3ed1e8a0 /src/mainboard
parente86ded841fdb3846b070a9cbe1793f72efe540aa (diff)
downloadcoreboot-13746076e95a611b56dfe37519685ae125172bb4.tar.xz
mainboard/(i945,ich7): Remove commented RCBA32(0x341c) code
PCIe root port clock gate is already enabled at i945/early_init.c Also fix comments when only PCIe root port is enabled. Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asus/p5gc-mx/early_init.c2
-rw-r--r--src/mainboard/getac/p470/early_init.c3
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c2
-rw-r--r--src/mainboard/ibase/mb899/early_init.c3
-rw-r--r--src/mainboard/intel/d945gclf/early_init.c3
5 files changed, 2 insertions, 11 deletions
diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c
index 6d37fed2ef..988d2328f6 100644
--- a/src/mainboard/asus/p5gc-mx/early_init.c
+++ b/src/mainboard/asus/p5gc-mx/early_init.c
@@ -94,7 +94,7 @@ static u8 msr_get_fsb(void)
void mainboard_late_rcba_config(void)
{
- /* Enable PCIe Root Port Clock Gate */
+ /* Enable only PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c
index c75caada6e..1ce44ae9d7 100644
--- a/src/mainboard/getac/p470/early_init.c
+++ b/src/mainboard/getac/p470/early_init.c
@@ -138,9 +138,6 @@ void mainboard_late_rcba_config(void)
/* Disable unused devices */
RCBA32(FD) |= FD_INTLAN;
- /* Enable PCIe Root Port Clock Gate */
- // RCBA32(0x341c) = 0x00000001;
-
/* This should probably go into the ACPI enable trap */
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c
index 7b82059580..f0f598b7af 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c
@@ -56,6 +56,6 @@ void bootblock_mainboard_early_init(void)
void mainboard_late_rcba_config(void)
{
- /* Enable PCIe Root Port Clock Gate */
+ /* Enable only PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c
index 0b005022d8..fd96f66ea8 100644
--- a/src/mainboard/ibase/mb899/early_init.c
+++ b/src/mainboard/ibase/mb899/early_init.c
@@ -110,7 +110,4 @@ void mainboard_late_rcba_config(void)
RCBA16(D29IR) = 0x0237;
RCBA16(D28IR) = 0x3201;
RCBA16(D27IR) = 0x0146;
-
- /* Enable PCIe Root Port Clock Gate */
- // RCBA32(0x341c) = 0x00000001;
}
diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c
index b4818e49ca..d31fcc5907 100644
--- a/src/mainboard/intel/d945gclf/early_init.c
+++ b/src/mainboard/intel/d945gclf/early_init.c
@@ -32,9 +32,6 @@ void mainboard_late_rcba_config(void)
/* Disable unused devices */
RCBA32(FD) |= FD_INTLAN;
-
- /* Enable PCIe Root Port Clock Gate */
- // RCBA32(0x341c) = 0x00000001;
}
void bootblock_mainboard_early_init(void)