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| author | Wisley <wisley.chen@quantatw.com> | 2015-11-24 20:12:36 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:23:21 +0100 |
| commit | 1a8e43e4e3e081e8e6c9037bbef4a7a18a181309 (patch) | |
| tree | ef2a00cb1e392abfd9d3f19ff00aed4a146695d0 /src/mainboard | |
| parent | 8c83c65ef3a5346c30c88c8d7d088be6b84c6756 (diff) | |
| download | coreboot-1a8e43e4e3e081e8e6c9037bbef4a7a18a181309.tar.xz | |
google/chell: update dptf TSR1 & TSR2 critial points
update dptf TSR1 & TSR2 critial points from 70 to 75
TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT
test, change the point will avoid to trigger critial in our factory
run in test
BRANCH=none
BUG=none
TEST=build and boot chell DUT
Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb
Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca
Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313967
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/12604
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/chell/acpi/dptf.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index 45783dcf40..c8362b7c28 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -25,12 +25,12 @@ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "Charger" #define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_CRITICAL 75 #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "DRAM" #define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_NAME "WiFi" |