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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-09-27 11:51:23 +0200
committerWerner Zeh <werner.zeh@siemens.com>2018-10-01 04:14:41 +0000
commit1e67f0773bff13b6ced9e9cf101917538f49c48b (patch)
tree803f2d450d3ac81af736d042e99fc3aeb05f2429 /src/mainboard
parent15d840558480536ddaca71bc1876254d59fca7fe (diff)
downloadcoreboot-1e67f0773bff13b6ced9e9cf101917538f49c48b.tar.xz
siemens/mc_apl1: Activate clock spreading for PTN3460
In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28761 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
index f1cbf0f0ee..829af2a25b 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c
@@ -84,8 +84,8 @@ int ptn3460_init(const char *hwi_block)
/* Use 18 bits per pixel. */
cfg.lvds_interface_ctrl1 |= 0x20;
- /* No clock spreading, 300 mV LVDS swing. */
- cfg.lvds_interface_ctrl2 = 0x03;
+ /* 1 % clock spreading, 300 mV LVDS swing. */
+ cfg.lvds_interface_ctrl2 = 0x13;
/* No LVDS signal swap. */
cfg.lvds_interface_ctrl3 = 0x00;
/* Delay T2 (VDD to LVDS active) by 16 ms. */