diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2018-04-23 20:02:35 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-04-26 17:52:43 +0000 |
| commit | 42ae0baead33b830bb82e993bdbdabdfedc356b0 (patch) | |
| tree | 79479b7858957d82ff094fcde862c3832aadbe1c /src/mainboard | |
| parent | a96e31b469c726563812158c4520f67aa6e128d7 (diff) | |
| download | coreboot-42ae0baead33b830bb82e993bdbdabdfedc356b0.tar.xz | |
mb/lenovo/x200: Use acpi_s3_resume_allowed()
Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed())
also to the Lenovo X200.
Change-Id: I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index d8ed0391e1..71de5504db 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -89,16 +89,16 @@ void mainboard_romstage_entry(unsigned long bist) /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } } /* RAM initialization */ |