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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-17 18:08:40 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-14 22:37:23 +0100 |
| commit | 486c05f4bfea71b6a5cbb216272199b2ad1dca02 (patch) | |
| tree | c922a87a8f3205afb7a2d7fa06debb90518f6354 /src/mainboard | |
| parent | 11f9c35bd20839d79d1b35d3ecde29a5e8132781 (diff) | |
| download | coreboot-486c05f4bfea71b6a5cbb216272199b2ad1dca02.tar.xz | |
AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration
A set of pins can be configured for GPIO or (parallel) PCI bridge use.
When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.
When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.
As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.
Drop related dead code.
Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/asus/m5a88-v/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/mainboard.c | 4 |
3 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 9b6450d09e..90d3342faa 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -37,10 +37,6 @@ void enable_int_gfx(void) { volatile u8 *gpio_reg; -#ifdef UNUSED_CODE - RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */ - RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ -#endif /* make sure the Acpi MMIO(fed80000) is accessible */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 8ee338efc9..9be0ce99d2 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -37,10 +37,6 @@ void enable_int_gfx(void) { volatile u8 *gpio_reg; -#ifdef UNUSED_CODE - RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */ - RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */ -#endif /* make sure the MMIO(fed80000) is accessible */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469e78..0f5f7446a8 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -37,10 +37,6 @@ void enable_int_gfx(void) { volatile u8 *gpio_reg; -#ifdef UNUSED_CODE - RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */ - RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ -#endif /* make sure the Acpi MMIO(fed80000) is accessible */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); |