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authorCaveh Jalali <caveh@chromium.org>2018-01-11 20:12:39 -0800
committerShelley Chen <shchen@google.com>2018-01-22 21:49:45 +0000
commit50657aa48e3a8e108b5769374a9852b0d4d1417f (patch)
tree9485bbccac61f5de31c80e99bef56b1c3211d815 /src/mainboard
parent7ea8e02f4b948c0a59648d59a0ffe53d1be40cd3 (diff)
downloadcoreboot-50657aa48e3a8e108b5769374a9852b0d4d1417f.tar.xz
mainboard/google/zoombini: add EC to ACPI tables
this adds missing ACPI entries for the EC, CPU, and power button. also, the EC to AP wakeup pin assignment is fixed. BUG=b:71819257 BRANCH=chromeos-2016.05 TEST=booted on meowth. /sys/class/power_supply now gets populated. Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/23237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/zoombini/dsdt.asl19
-rw-r--r--src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h2
2 files changed, 20 insertions, 1 deletions
diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl
index c50a79ae42..e892b47fae 100644
--- a/src/mainboard/google/zoombini/dsdt.asl
+++ b/src/mainboard/google/zoombini/dsdt.asl
@@ -15,6 +15,9 @@
* GNU General Public License for more details.
*/
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -30,7 +33,14 @@ DefinitionBlock(
// global NVS and variables
#include <soc/intel/cannonlake/acpi/globalnvs.asl>
+ // CPU
+ #include <soc/intel/cannonlake/acpi/cpu.asl>
+
Scope (\_SB) {
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
Device (PCI0)
{
#include <soc/intel/cannonlake/acpi/northbridge.asl>
@@ -45,4 +55,13 @@ DefinitionBlock(
// Chipset specific sleep states
#include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
}
diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
index e1b566d8a1..ea48e62c57 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
@@ -32,7 +32,7 @@
#define GPIO_PCH_WP GPP_A1
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE GPP_74
+#define GPE_EC_WAKE GPE0_LAN_WAK
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI