check in the current code for IBM/E325, can somebody help to fix it ?

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 54 insertions, 175 deletions

diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index bd9df2e3ac..6c2f7fa718 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -44,8 +44,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 			bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
-		}
-		else {
+		} else {
 			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
 
 			bus_8111_1 = 4;
@@ -55,20 +54,15 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 		dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
 		if (dev) {
 			bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
+		} else {
 			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
-
 			bus_8131_1 = 2;
 		}
 		/* 8131-2 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
 		if (dev) {
 			bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
+		} else {
 			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
 
 			bus_8131_2 = 3;
@@ -82,19 +76,18 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	smp_write_bus(mc, bus_isa, "ISA	  ");
 
 	/* IOAPIC handling */
-
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
 	{
 		device_t dev;
 		uint32_t base;
-		/* 8131 apic 3 */
+		/* 8131-1 apic #3 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
 		if (dev) {
 			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			base &= PCI_BASE_ADDRESS_MEM_MASK;
 			smp_write_ioapic(mc, 0x03, 0x11, base);
 		}
-		/* 8131 apic 4 */
+		/* 8131-2 apic #4 */
 		dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
 		if (dev) {
 			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -143,46 +136,34 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 		bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
+	/* PCI Ints:	     Type	Polarity	       Trigger			Bus ID      PCIDEVNUM|IRQ  APIC ID PIN# */
+	/* On board nics */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, 0x02, 0x13);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, 0x02, 0x13);
 
 	/* PCI Slot 1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (1<<2)|0, 0x02, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (1<<2)|1, 0x02, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (1<<2)|2, 0x02, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (1<<2)|3, 0x02, 0x10);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, 0x02, 0x11);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, 0x02, 0x12);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, 0x02, 0x13);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, 0x02, 0x10);
 
 	/* PCI Slot 2 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (2<<2)|0, 0x02, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (2<<2)|1, 0x02, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (2<<2)|2, 0x02, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_2, (2<<2)|3, 0x02, 0x11);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, 0x02, 0x12);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, 0x02, 0x13);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, 0x02, 0x10);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, 0x02, 0x11);
 
 	/* PCI Slot 3 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (1<<2)|0, 0x02, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (1<<2)|1, 0x02, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (1<<2)|2, 0x02, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (1<<2)|3, 0x02, 0x10);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x02, 0x11);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x02, 0x12);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, 0x02, 0x13);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, 0x02, 0x10);
 
 	/* PCI Slot 4 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (2<<2)|0, 0x02, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (2<<2)|1, 0x02, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (2<<2)|2, 0x02, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (2<<2)|3, 0x02, 0x11);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|0, 0x02, 0x12);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|1, 0x02, 0x13);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|2, 0x02, 0x10);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|3, 0x02, 0x11);
 
 	/* PCI Slot 5 */
 #warning "FIXME get the irqs right, it's just hacked to work for now"
@@ -206,20 +187,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 		bus_8111_1, (4<<2)|3, 0x02, 0x13);
 
-	/* On board nics */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (3<<2)|0, 0x02, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_8131_1, (4<<2)|0, 0x02, 0x13);
-
 	/* There is no extension information... */
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 	printk_debug("Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
+		     mc, smp_next_mpe_entry(mc));
 	return smp_next_mpe_entry(mc);
 }
 
diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb
index b485747caf..70be773450 100644
--- a/src/mainboard/ibm/e325/Config.lb
+++ b/src/mainboard/ibm/e325/Config.lb
@@ -258,13 +258,13 @@ northbridge amd/amdk8 "mc0"
 	pci 0:18.1
 	pci 0:18.2
 	pci 0:18.3
-	southbridge amd/amd8131 "amd8131" link 0
+	southbridge amd/amd8131 "amd8131" link 1
 		pci 0:0.0
 		pci 0:0.1
 		pci 0:1.0
 		pci 0:1.1
 	end
-	southbridge amd/amd8111 "amd8111" link 0
+	southbridge amd/amd8111 "amd8111" link 1
 		pci 0:0.0
 		pci 0:1.0 on
 		pci 0:1.1 on
@@ -314,7 +314,7 @@ northbridge amd/amdk8 "mc1"
 end
 
 cpu k8 "cpu0"
-	register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
+	register "across" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
 end
 
 cpu k8 "cpu1" 
diff --git a/src/mainboard/ibm/e325/auto.c b/src/mainboard/ibm/e325/auto.c
index 7dd1fbde17..ed78fe3d7a 100644
--- a/src/mainboard/ibm/e325/auto.c
+++ b/src/mainboard/ibm/e325/auto.c
@@ -173,19 +173,20 @@ static void main(void)
 	console_init();
 	setup_ibm_e325_resource_map();
 	needs_reset = setup_coherent_ht_domain();
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
 	if (needs_reset) {
 		print_info("ht reset -\r\n");
 		soft_reset();
 	}
 
-#if 0
+#if 1
 	print_pci_devices();
 #endif
 	enable_smbus();
 #if 0
 	dump_spd_registers(&cpu[0]);
 #endif
+
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
@@ -196,7 +197,6 @@ static void main(void)
 	dump_pci_device(PCI_DEV(0, 0x18, 2));
 #endif
 
-
 #if 0
 	/* Check the first 1M */
 	ram_check(0x00000000, 0x001000000);
diff --git a/src/mainboard/ibm/e325/mainboard.c b/src/mainboard/ibm/e325/mainboard.c
index bbc6f53716..e526a78a75 100644
--- a/src/mainboard/ibm/e325/mainboard.c
+++ b/src/mainboard/ibm/e325/mainboard.c
@@ -281,6 +281,6 @@ static void enumerate(struct chip *chip)
 }
 struct chip_control mainboard_arima_hdama_control = {
 	.enumerate = enumerate, 
-	.name      = "Arima HDAMA mainboard ",
+	.name      = "IBM E325 mainboard ",
 };
 
diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c
index efeaf6e087..044a5d96f4 100644
--- a/src/mainboard/ibm/e325/resourcemap.c
+++ b/src/mainboard/ibm/e325/resourcemap.c
@@ -1,103 +1,3 @@
-#if 0
-=================== CPU0 ===================
-RAM 0x0(0x3,0x3f0000):
-	0x000:0x3f00(no interleave, bogus), CP0, s: WE
-RAM 0x1(0x400003,0x7f0001):
-	0x4000:0x7f00(no interleave, bogus), CP1, s: WE
-RAM 0x2(0x800000,0x2):
-	0x8000:0x000(no interleave, bogus), CP2, s: NO WE
-RAM 0x3(0x800000,0x3):
-	0x8000:0x000(no interleave, bogus), CP3, s: NO WE
-RAM 0x4(0x800000,0x4):
-	0x8000:0x000(no interleave, bogus), CP4, s: NO WE
-RAM 0x5(0x800000,0x5):
-	0x8000:0x000(no interleave, bogus), CP5, s: NO WE
-RAM 0x6(0x800000,0x6):
-	0x8000:0x000(no interleave, bogus), CP6, s: NO WE
-RAM 0x7(0x800000,0x7):
-	0x8000:0x000(no interleave, bogus), CP7, s: NO WE
-MMIO 0x0(0xfc0003,0xfe2f10):
-	0xfc000000:0xfe2f0000, HT1 CP0,   WE:RE
-MMIO 0x1(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-MMIO 0x2(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-MMIO 0x3(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-MMIO 0x4(0xfec003,0xfec010):
-	0xfec00000:0xfec00000, HT1 CP0,   WE:RE
-MMIO 0x5(0xa03,0xb10):
-	0xa0000:0xb0000, HT1 CP0,   WE:RE
-MMIO 0x6(0xfed003,0xfed010):
-	0xfed00000:0xfed00000, HT1 CP0,   WE:RE
-MMIO 0x7(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-PCIO 0x0(0x33,0x1fff010):
-	0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
-PCIO 0x1(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-PCIO 0x2(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-PCIO 0x3(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-CONF 0x0(0xff000103):
-	0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
-CONF 0x1(0xffff0060):
-	0xff0000:0x00000, HT0 CP6, Dev number compare enable NO WE:NO RE
-CONF 0x2(0xffff0324):
-	0xff0000:0x00000, HT3 CP2, Dev number compare enable NO WE:NO RE
-CONF 0x3(0xffff0204):
-	0xff0000:0x00000, HT2 CP0, Dev number compare enable NO WE:NO RE
-=================== CPU1 ===================
-RAM 0x0(0x3,0x3f0000):
-	0x000:0x3f00(no interleave, bogus), CP0, s: WE
-RAM 0x1(0x400003,0x7f0001):
-	0x4000:0x7f00(no interleave, bogus), CP1, s: WE
-RAM 0x2(0x800000,0x2):
-	0x8000:0x000(no interleave, bogus), CP2, s: NO WE
-RAM 0x3(0x800000,0x3):
-	0x8000:0x000(no interleave, bogus), CP3, s: NO WE
-RAM 0x4(0x800000,0x4):
-	0x8000:0x000(no interleave, bogus), CP4, s: NO WE
-RAM 0x5(0x800000,0x5):
-	0x8000:0x000(no interleave, bogus), CP5, s: NO WE
-RAM 0x6(0x800000,0x6):
-	0x8000:0x000(no interleave, bogus), CP6, s: NO WE
-RAM 0x7(0x800000,0x7):
-	0x8000:0x000(no interleave, bogus), CP7, s: NO WE
-MMIO 0x0(0xfc0003,0xfe2f10):
-	0xfc000000:0xfe2f0000, HT1 CP0,   WE:RE
-MMIO 0x1(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-MMIO 0x2(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-MMIO 0x3(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-MMIO 0x4(0xfec003,0xfec010):
-	0xfec00000:0xfec00000, HT1 CP0,   WE:RE
-MMIO 0x5(0xa03,0xb10):
-	0xa0000:0xb0000, HT1 CP0,   WE:RE
-MMIO 0x6(0xfed003,0xfed010):
-	0xfed00000:0xfed00000, HT1 CP0,   WE:RE
-MMIO 0x7(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-PCIO 0x0(0x33,0x1fff010):
-	0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
-PCIO 0x1(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-PCIO 0x2(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-PCIO 0x3(0x0,0x0):
-	0x00000:0x00000, HT0 CP0,   NO WE:NO RE
-CONF 0x0(0xff000103):
-	0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
-CONF 0x1(0xffff0200):
-	0xff0000:0x00000, HT2 CP0,  NO WE:NO RE
-CONF 0x2(0xffff0370):
-	0xff0000:0x00000, HT3 CP7, Dev number compare enable NO WE:NO RE
-CONF 0x3(0xffff0330):
-	0xff0000:0x00000, HT3 CP3, Dev number compare enable NO WE:NO RE
-#endif
 /*
  * IBM E325 needs a different resource map
  *
@@ -237,22 +137,27 @@ static void setup_ibm_e325_resource_map(void)
 	 *	   This field defines the upper address bits of a 40bit address 
 	 *	   that defines the start of memory-mapped I/O region i
 	 */
-	PCI_ADDR(0, 0x18, 1,  0xbc), 0x48, 0xfe2f10, 
-	PCI_ADDR(0, 0x18, 1,  0xb8), 0xf0, 0xfc0003, 
-	PCI_ADDR(0, 0x18, 1,  0xbc), 0x48, 0xfec010, 
-	PCI_ADDR(0, 0x18, 1,  0xb8), 0xf0, 0xfec003, 
-	PCI_ADDR(0, 0x18, 1,  0xbc), 0x48, 0xb10, 
-	PCI_ADDR(0, 0x18, 1,  0xb8), 0xf0, 0xa03, 
-	PCI_ADDR(0, 0x18, 1,  0xbc), 0x48, 0xfed010, 
-	PCI_ADDR(0, 0x18, 1,  0xb8), 0xf0, 0xfed003, 
-	PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0, 
-	PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0, 
+
+	PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
+	PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
+	//PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
+	// PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
+
+	PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010, 
+	PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003, 
+	//PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
+	//PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
+
+	PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
+	PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
+	//PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
+	//PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
+
+	PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010, 
+	PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
+	//PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
+	//PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
+
 	PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0, 
 	PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0, 
 	PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,