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authorJulius Werner <jwerner@chromium.org>2018-08-10 16:13:26 -0700
committerJulius Werner <jwerner@chromium.org>2018-08-17 21:29:46 +0000
commit5d6593a43c728a9d526a3cb0026048bf335830d4 (patch)
tree973e093b9daf4edd1c6b6a13b70ba97cce6483d3 /src/mainboard
parent2d22cda32c5b9f21ab0c7271bc88a2472fc0fda2 (diff)
downloadcoreboot-5d6593a43c728a9d526a3cb0026048bf335830d4.tar.xz
arm64: Factor out common parts of romstage execution flow
The romstage main() entry point on arm64 boards is usually in mainboard code, but there are a handful of lines that are always needed in there and not really mainboard specific (or chipset specific). We keep arguing every once in a while that this isn't ideal, so rather than arguing any longer let's just fix it. This patch moves the main() function into arch code with callbacks that the platform can hook into. (This approach can probably be expanded onto other architectures, so when that happens this file should move into src/lib.) Tested on Cheza and Kevin. I think the approach is straight-forward enough that we can take this without testing every board. (Note that in a few cases, this delays some platform-specific calls until after console_init() and exception_init()... since these functions don't really take that long, especially if there is no serial console configured, I don't expect this to cause any issues.) Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/cavium/cn8100_sff_evb/romstage.c14
-rw-r--r--src/mainboard/google/cheza/romstage.c13
-rw-r--r--src/mainboard/google/gru/romstage.c18
-rw-r--r--src/mainboard/google/kukui/romstage.c15
-rw-r--r--src/mainboard/google/oak/romstage.c31
5 files changed, 12 insertions, 79 deletions
diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
index e8e5cd6f90..7bb53e3de3 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c
@@ -14,34 +14,24 @@
*
*/
-#include <arch/exception.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
+#include <arch/stages.h>
#include <soc/sdram.h>
#include <soc/timer.h>
#include <soc/mmu.h>
#include <stdlib.h>
-#include <console/console.h>
-#include <program_loading.h>
#include <libbdk-hal/bdk-config.h>
#include <string.h>
extern const struct bdk_devicetree_key_value devtree[];
-void main(void)
+void platform_romstage_main(void)
{
watchdog_poke(0);
- console_init();
- exception_init();
-
bdk_config_set_fdt(devtree);
sdram_init();
soc_mmu_init();
watchdog_poke(0);
-
- cbmem_initialize_empty();
- run_ramstage();
}
diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c
index c930016080..ad8506193d 100644
--- a/src/mainboard/google/cheza/romstage.c
+++ b/src/mainboard/google/cheza/romstage.c
@@ -13,17 +13,8 @@
* GNU General Public License for more details.
*/
-#include <arch/exception.h>
-#include <cbmem.h>
-#include <halt.h>
-#include <program_loading.h>
-#include <console/console.h>
-#include <timestamp.h>
+#include <arch/stages.h>
-void main(void)
+void platform_romstage_main(void)
{
- console_init();
- exception_init();
- cbmem_initialize_empty();
- run_ramstage();
}
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index 9f938f3eb2..edf440d00e 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -14,24 +14,14 @@
*
*/
-#include <arch/cache.h>
-#include <arch/cpu.h>
-#include <arch/exception.h>
#include <arch/mmu.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <gpio.h>
-#include <console/console.h>
+#include <arch/stages.h>
#include <delay.h>
-#include <program_loading.h>
-#include <romstage_handoff.h>
-#include <soc/addressmap.h>
#include <soc/mmu_operations.h>
#include <soc/tsadc.h>
#include <soc/sdram.h>
#include <symbols.h>
#include <soc/usb.h>
-#include <stdlib.h>
#include "board.h"
#include "pwm_regulator.h"
@@ -70,11 +60,9 @@ static void prepare_usb(void)
reset_usb_otg1();
}
-void main(void)
+void platform_romstage_main(void)
{
- console_init();
tsadc_init(TSHUT_POL_HIGH);
- exception_init();
/* Init DVS to conservative values. */
init_dvs_outputs();
@@ -87,6 +75,4 @@ void main(void)
mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB,
CACHED_MEM);
mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
- cbmem_initialize_empty();
- run_ramstage();
}
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 342a0ba3d2..9eeaa68e09 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -13,21 +13,10 @@
* GNU General Public License for more details.
*/
-#include <arch/exception.h>
-#include <console/console.h>
-#include <program_loading.h>
+#include <arch/stages.h>
#include <soc/mmu_operations.h>
-#include <timestamp.h>
-void main(void)
+void platform_romstage_main(void)
{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- /* Init UART baudrate when PLL on. */
- console_init();
- exception_init();
-
mtk_mmu_after_dram();
-
- run_ramstage();
}
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index 9f5ce5f2df..754c40ce66 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -12,39 +12,21 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <arch/cache.h>
-#include <arch/cpu.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/mmu.h>
-#include <boardid.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <romstage_handoff.h>
-#include <symbols.h>
-#include <timer.h>
-#include <timestamp.h>
+#include <arch/stages.h>
+#include <boardid.h>
#include <soc/emi.h>
#include <soc/mmu_operations.h>
#include <soc/mt6391.h>
#include <soc/pll.h>
#include <soc/rtc.h>
+#include <timer.h>
-void main(void)
+void platform_romstage_main(void)
{
int stabilize_usec;
struct stopwatch sw;
- timestamp_add_now(TS_START_ROMSTAGE);
-
- /* init uart baudrate when pll on */
- console_init();
- exception_init();
-
rtc_boot();
/* Raise CPU voltage to allow higher frequency */
@@ -64,9 +46,4 @@ void main(void)
mt_pll_raise_ca53_freq(1700 * MHz);
mtk_mmu_after_dram();
-
- /* should be called after memory init */
- cbmem_initialize_empty();
-
- run_ramstage();
}