diff options
| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-03-17 01:47:25 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-03-17 01:47:25 +0000 |
| commit | 5d6645ae4435337fd55e60f62daab2e3b372351e (patch) | |
| tree | 94d8fd5ca0a547d67ad31b449bc1df3c77da4e64 /src/mainboard | |
| parent | 4d01bd580944540bde6c833f444f55c92c2abe54 (diff) | |
| download | coreboot-5d6645ae4435337fd55e60f62daab2e3b372351e.tar.xz | |
- TOM2 is filled in by the dynamic ACPI code. Don't hardcode it in the
DSDT and use the dynamic TOM2 variable instead.
- The DSDT needs to be revision 2 or above to handle 64 bit variables.
This will require a recent (not older than 2007) iasl (ACPI compiler).
- Fix an incorrect comment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/dbm690t/acpi/dsdt.asl | 6 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/acpi/dsdt.asl | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/amd/dbm690t/acpi/dsdt.asl b/src/mainboard/amd/dbm690t/acpi/dsdt.asl index bc5d6ffa53..5c10d82ea7 100644 --- a/src/mainboard/amd/dbm690t/acpi/dsdt.asl +++ b/src/mainboard/amd/dbm690t/acpi/dsdt.asl @@ -21,7 +21,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x01, /* DSDT Revision */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ "DBM690T ", /* TABLE ID */ 0x00010001 /* OEM Revision */ @@ -32,7 +32,6 @@ DefinitionBlock ( /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ /* Memory related values */ - Name(TOM2, 0x0) /* Top of RAM memory above 4GB (>> 16) */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ @@ -1130,6 +1129,7 @@ DefinitionBlock ( /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) + External (TOM2) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1476,7 +1476,7 @@ DefinitionBlock ( 0x0000, /* range minimum */ 0x0CF7, /* range maximum */ 0x0000, /* translation */ - 0x0CF8 /* Resource source index */ + 0x0CF8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/amd/pistachio/acpi/dsdt.asl b/src/mainboard/amd/pistachio/acpi/dsdt.asl index 3cca39c324..3c85a84392 100644 --- a/src/mainboard/amd/pistachio/acpi/dsdt.asl +++ b/src/mainboard/amd/pistachio/acpi/dsdt.asl @@ -21,7 +21,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x01, /* DSDT Revision */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ "PISTACHI", /* TABLE ID */ 0x00010001 /* OEM Revision */ @@ -32,7 +32,6 @@ DefinitionBlock ( /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ /* Memory related values */ - Name(TOM2, 0x0) /* Top of RAM memory above 4GB (>> 16) */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ @@ -1129,6 +1128,7 @@ DefinitionBlock ( /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) + External (TOM2) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1399,7 +1399,7 @@ DefinitionBlock ( 0x0000, /* range minimum */ 0x0CF7, /* range maximum */ 0x0000, /* translation */ - 0x0CF8 /* Resource source index */ + 0x0CF8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |