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authorJulius Werner <jwerner@chromium.org>2018-11-26 17:16:24 -0800
committerJulius Werner <jwerner@chromium.org>2018-12-14 21:09:20 +0000
commit5d7f5bc973f4aac3e2833baba7e6e386c602f5b4 (patch)
tree78d80bb7f9a675d530f2db1db1abf0d099cc4c61 /src/mainboard
parent674c62bbee60e05b5830f3b4db85341d130d3d1f (diff)
downloadcoreboot-5d7f5bc973f4aac3e2833baba7e6e386c602f5b4.tar.xz
cheza: Add board reset via Chrome EC
This patch implements board reset on the Cheza board. The real board reset used by the operating system uses the PMIC, but unfortunately the PMIC needs to be configured right for that to work. The PMIC configuration currently happens in the Qualcomm blob (QcLib) that is run from romstage, but vboot needs to be able to reboot during verstage already. Porting all the PMIC initialization code to run in the bootblock seems excessive (and at odds with the goal of doing as little as possible before verification), so we'll just do a little hack and ask the EC to perform a cold reset instead. For vboot purposes, this should work just as well. BUG=b:118501305 TEST=Hacked vboot code to call vboot_reboot(), confirmed that board reset and came back up as expected. Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/29849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/cheza/Kconfig1
-rw-r--r--src/mainboard/google/cheza/Makefile.inc4
-rw-r--r--src/mainboard/google/cheza/reset.c24
3 files changed, 28 insertions, 1 deletions
diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig
index b940314acb..59f78a8e56 100644
--- a/src/mainboard/google/cheza/Kconfig
+++ b/src/mainboard/google/cheza/Kconfig
@@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS
select SPI_FLASH
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_CHROMEOS
- select MISSING_BOARD_RESET
select MAINBOARD_HAS_TPM2
select MAINBOARD_HAS_SPI_TPM_CR50
diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc
index 04099e2033..ff94b76377 100644
--- a/src/mainboard/google/cheza/Makefile.inc
+++ b/src/mainboard/google/cheza/Makefile.inc
@@ -17,17 +17,21 @@ bootblock-y += boardid.c
bootblock-y += memlayout.ld
bootblock-y += chromeos.c
bootblock-y += bootblock.c
+bootblock-y += reset.c
verstage-y += boardid.c
verstage-y += memlayout.ld
verstage-y += chromeos.c
+verstage-y += reset.c
romstage-y += boardid.c
romstage-y += memlayout.ld
romstage-y += chromeos.c
romstage-y += romstage.c
+romstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += memlayout.ld
ramstage-y += chromeos.c
ramstage-y += mainboard.c
+ramstage-y += reset.c
diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c
new file mode 100644
index 0000000000..b3cd192ec5
--- /dev/null
+++ b/src/mainboard/google/cheza/reset.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include <reset.h>
+
+/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
+ but this works well enough for our purposes. */
+void do_board_reset(void)
+{
+ google_chromeec_reboot(0, EC_REBOOT_COLD, 0);
+}