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authorGabe Black <gabeblack@google.com>2012-03-29 17:58:52 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2012-05-01 07:24:16 +0200
commit5fe7a209f5cc6a713014b5d20b33a907ab3fb8c1 (patch)
tree62a44e79ea042b6035ba3cdbf3d9cb40766da9ec /src/mainboard
parentbea842114514d88d5499d42597d8d692d29af1c2 (diff)
downloadcoreboot-5fe7a209f5cc6a713014b5d20b33a907ab3fb8c1.tar.xz
Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.
This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my best interpretation of the schematic. It may not be correct, but it doesn't seem to cause any problems either. Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/emeraldlake2/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 2631cfcdcf..686fe2e347 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -45,8 +45,10 @@ chip northbridge/intel/sandybridge
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
- register "gpi1_routing" = "0"
+ register "gpi1_routing" = "1"
register "gpi14_routing" = "2"
+ register "alt_gp_smi_en" = "0x0002"
+ register "gpe0_en" = "0x4000"
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"