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| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-16 22:46:57 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-26 02:06:45 +0000 |
| commit | 662da6cf7b181ea2787ba001d9cbb6d41916abec (patch) | |
| tree | 63a95b276913110c423c566db78b856650582ad3 /src/mainboard | |
| parent | a1b15172d7f0303e8a1fe147a778d73d4dc26b1a (diff) | |
| download | coreboot-662da6cf7b181ea2787ba001d9cbb6d41916abec.tar.xz | |
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/ocp/tiogapass/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/ocp/tiogapass/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/ocp/tiogapass/dsdt.asl | 4 |
3 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 9dbc066f10..1d501e6db0 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -19,10 +19,9 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 - select FSP_CAR select IPMI_KCS + select SOC_INTEL_SKYLAKE_SP config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index c2eddf270c..51e6a62eb1 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -chip soc/intel/xeon_sp +chip soc/intel/xeon_sp/skx register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 41c006bc92..9d33865271 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -28,12 +28,12 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/xeon_sp/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> // Xeon-SP ACPI tables Scope (\_SB) { - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } } |