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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2019-05-28 23:49:32 +0800
committerFurquan Shaikh <furquan@google.com>2019-05-29 18:48:10 +0000
commit702f83897730739af21d10649759589ae9a22203 (patch)
tree4b5e505a1c0cf78ddab721bd1dd7855cd7cfc8e1 /src/mainboard
parentc30e59051fcbda4fba8a2c36c6b04110ee1caacd (diff)
downloadcoreboot-702f83897730739af21d10649759589ae9a22203.tar.xz
mb/google/sarien: Send post code to the EC
Use the mainboard post code hook to inform the wilco EC driver of the every stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/Makefile.inc5
-rw-r--r--src/mainboard/google/sarien/ec.c23
-rw-r--r--src/mainboard/google/sarien/ramstage.c6
3 files changed, 28 insertions, 6 deletions
diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc
index 6fd23cefcd..7c37bc9901 100644
--- a/src/mainboard/google/sarien/Makefile.inc
+++ b/src/mainboard/google/sarien/Makefile.inc
@@ -29,5 +29,10 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c
+ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c
+romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c
+verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c
+
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c
new file mode 100644
index 0000000000..fd8e84fbc8
--- /dev/null
+++ b/src/mainboard/google/sarien/ec.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <ec/google/wilco/commands.h>
+#include <variant/ec.h>
+
+void mainboard_post(uint8_t value)
+{
+ wilco_ec_save_post_code(value);
+}
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index e246419373..1d220461cf 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -15,7 +15,6 @@
#include <arch/acpi.h>
#include <drivers/vpd/vpd.h>
-#include <ec/google/wilco/commands.h>
#include <smbios.h>
#include <soc/gpio.h>
#include <soc/ramstage.h>
@@ -70,11 +69,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
cnl_configure_pads(gpio_table, num_gpios);
}
-void mainboard_post(uint8_t value)
-{
- wilco_ec_save_post_code(value);
-}
-
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;