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authorRonak Kanabar <ronak.kanabar@intel.com>2020-05-11 10:37:15 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-12 20:06:26 +0000
commit727fe925649cadc2803e56b8d5ddb070ddc36a43 (patch)
tree53654850f8b3bf7c56131e12e0cd1fd78b67eea1 /src/mainboard
parent511aa44ee68bba15f3aa87e0b6766852436a1c65 (diff)
downloadcoreboot-727fe925649cadc2803e56b8d5ddb070ddc36a43.tar.xz
mb/intel/jasperlake_rvp: Remove SataEnable deviceetree config
SataEnable UPD override will be filled using devicetree pci device status check. Change-Id: I957dfcf139acd4f4dd5723bc1b010ec45ec91651 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41227 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 61ce6cca2b..1e88c7ae62 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -86,8 +86,6 @@ chip soc/intel/jasperlake
register "PcieClkSrcClkReq[4]" = "0x04"
register "PcieClkSrcClkReq[5]" = "0x05"
- register "SataEnable" = "0"
-
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,