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authorNathan_chen <Nathan_chen@wistron.corp-partner.google.com>2019-04-23 21:53:27 +0800
committerDuncan Laurie <dlaurie@chromium.org>2019-04-24 15:53:26 +0000
commit77fb3632a4a3d3004b3aa4950967be9164d9711d (patch)
tree993ec4ae02ba5f7a8b7d67619154fa682b76a80e /src/mainboard
parentbb4759c15d210753e54d0568392c3c3871a37917 (diff)
downloadcoreboot-77fb3632a4a3d3004b3aa4950967be9164d9711d.tar.xz
mb/google/arcada: Add settings for noise mitgation
Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com> Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32403 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 57c4e65e70..426bdae88d 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -37,10 +37,10 @@ chip soc/intel/cannonlake
register "tdp_pl2_override" = "51"
register "Device4Enable" = "1"
register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRateForIa" = "0"
- register "SlowSlewRateForGt" = "0"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "0"
- register "SlowSlewRateForFivr" = "0"
+ register "SlowSlewRateForFivr" = "2"
# Enable eDP device
register "DdiPortEdp" = "1"
# Enable HPD for DDI ports B/C