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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-20 06:43:44 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-04-03 06:15:13 +0200
commit7a0aa9a4e0926b649d0c77aaeb7afd12d9f9f720 (patch)
tree60e2cddc1182e36bdd022c5fc95fe5711a598d47 /src/mainboard
parent92190198b04413a732d2f838be771ea032cd1d27 (diff)
downloadcoreboot-7a0aa9a4e0926b649d0c77aaeb7afd12d9f9f720.tar.xz
bap/ode_e20XX: Switch away from AGESA_LEGACY
Change-Id: I79d4a4d1d5966ab46c8a9b9e9ca4e09e21ecfea7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18717 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/bap/ode_e20XX/Kconfig1
-rw-r--r--src/mainboard/bap/ode_e20XX/romstage.c89
2 files changed, 8 insertions, 82 deletions
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index c89bf38522..6631ac8d71 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -18,7 +18,6 @@ if BOARD_ODE_E20XX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index cf92d0cb96..9921f368f4 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -15,37 +15,21 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81866d/f81866d.h>
-#include "cbmem.h"
+
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+ /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+ outb(0xea, 0xcd6);
+ outb(0x1, 0xcd7);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -53,62 +37,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
- int i;
- for(i = 0; i < 200000; i++)
- val = inb(0xcd6);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- prepare_for_resume();
- }
-
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
+ fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
}