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authorStefan Reinauer <stepan@coresystems.de>2010-08-30 16:52:48 +0000
committerStefan Reinauer <stepan@openbios.org>2010-08-30 16:52:48 +0000
commit849498d4471003ff959e0151828abfe9a7be4621 (patch)
tree26f4b2788cc5f98fbfb082b3268b58c59dcf0cb5 /src/mainboard
parent9a684fcb0fe28a47d23b7cb3acbd2add47c6ac50 (diff)
downloadcoreboot-849498d4471003ff959e0151828abfe9a7be4621.tar.xz
Fix intel mtarvon compilation by switching it over to CAR.
This should be unproblematic, as there are other boards with the same "socket" that work with CAR already. Tests are highly appreciated though! Acked-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/mtarvon/Kconfig10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 75cab8f23b..065d6d9de6 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I3100
select SOUTHBRIDGE_INTEL_I3100
select SUPERIO_INTEL_I3100
- select ROMCC
+ select USE_DCACHE_RAM
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@@ -34,6 +34,14 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x2680
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
config MAX_CPUS
int
default 4