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authorFurquan Shaikh <furquan@google.com>2019-04-10 22:39:15 -0700
committerSubrata Banik <subrata.banik@intel.com>2019-04-12 02:13:13 +0000
commit9007118f3239a4d2c9f3246d5744e4d7fdf6002a (patch)
treef3666c67d7a5ac7f81f5141a227fb0f22d2ef775 /src/mainboard
parent8f6f3ac199b77c5ec5ae1dee3b7dd4f03a60ea7e (diff)
downloadcoreboot-9007118f3239a4d2c9f3246d5744e4d7fdf6002a.tar.xz
mb/google/hatch: Skip UART0 config in FSP
UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=b:130325418 Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/variants/hatch/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
index 28644d14cf..b9ec1dd508 100644
--- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/cannonlake
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
- [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"