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authorDuncan Laurie <dlaurie@chromium.org>2013-11-04 11:22:27 -0800
committerAaron Durbin <adurbin@google.com>2014-04-30 23:08:35 +0200
commita90a59f5a3bfc22d6317186c004409469d1b031e (patch)
tree13752bef4bbf93dba2681eaa25034bd474835a5f /src/mainboard
parent81998090792ebc1a6e39455f5fcb4d2c9ec9c095 (diff)
downloadcoreboot-a90a59f5a3bfc22d6317186c004409469d1b031e.tar.xz
baytrail: Fix XHCI problems and re-enable
- a few clock gating bits were set improperly and were preventing the system from transitioning out of S0 state. - the XHCC registers were not getting the top byte set properly which includes things like DMA write request size and request boundary crossing control. This was causing memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot kernel from USB on rambi with XHCI driver Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4933 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/rambi/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index af115a6cbc..a5fe37ec4b 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -5,8 +5,8 @@ chip soc/intel/baytrail
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
- # Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
- register "usb_route_to_xhci" = "0"
+ # Route USB ports to XHCI
+ register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"