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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-01-31 17:46:29 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-02-01 10:12:12 +0100 |
| commit | ac1b6def75e8dd3cd792a55d85451fa6b43e472e (patch) | |
| tree | a8acd55cf9f3ab8906dd57bae9ad74530230a2f7 /src/mainboard | |
| parent | b26156ec65f1622f97d4439b3977c7880f234054 (diff) | |
| download | coreboot-ac1b6def75e8dd3cd792a55d85451fa6b43e472e.tar.xz | |
lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports.
Fixes USB3 ports degraded to USB2 speeds.
Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8313
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/lenovo/x230/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5130410e90..3a05b5a89a 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,6 +67,9 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported |