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authorGerd Hoffmann <kraxel@redhat.com>2013-09-17 10:35:43 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2013-09-18 12:07:02 +0200
commitad690f2e8182b182b4c343d2238bb079e6bb8db2 (patch)
tree1f0014864ba6751b4aca8afdd169e44d5becc6a9 /src/mainboard
parent3af0aa2533dc4dc7a0a11711c18587cee0104267 (diff)
downloadcoreboot-ad690f2e8182b182b4c343d2238bb079e6bb8db2.tar.xz
qemu: q35: fix pci bar placement
Without this coreboot may (depends on the amount of memory) place the pci bars below 0xb0000000, then the linux kernel goes move them around so they are inside the window declared in the acpi tables. This breaks vesafb as the vga framebuffer gets moved after vgabios initialization. It's also not exactly nice to expect the OS fix our mess ;) Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3927 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/emulation/qemu-i440fx/northbridge.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index a2cd37b37b..c87868925c 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -54,6 +54,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
{
u16 nbid = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
int i440fx = (nbid == 0x1237);
+ int q35 = (nbid == 0x29c0);
struct resource *res;
unsigned long tomk = 0, high;
int idx = 10;
@@ -89,6 +90,21 @@ static void cpu_pci_domain_read_resources(struct device *dev)
set_top_of_ram(tomk * 1024);
#endif
+ if (q35 && ((tomk * 1024) < 0xb0000000)) {
+ /*
+ * Reserve the region between top-of-ram and the
+ * mmconf xbar (ar 0xb0000000), so coreboot doesn't
+ * place pci bars there. The region isn't declared as
+ * pci io window in the acpi tables (\_SB.PCI0._CRS).
+ */
+ res = new_resource(dev, idx++);
+ res->base = tomk * 1024;
+ res->size = 0xb0000000 - tomk * 1024;
+ res->limit = 0xffffffff;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ }
+
if (i440fx) {
/* Reserve space for the IOAPIC. This should be in
* the southbridge, but I couldn't tell which device