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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-30 04:14:19 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-05 13:21:00 +0000
commitad787e18e0ed24495132d0e9e638ed835afad354 (patch)
tree9ee07a78a871830740879127c7c3f14094a57dd1 /src/mainboard
parent81ade745b19194fbad3e3d51d0dac6ca76de1f01 (diff)
downloadcoreboot-ad787e18e0ed24495132d0e9e638ed835afad354.tar.xz
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c7
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c7
2 files changed, 4 insertions, 10 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index cee7c2a603..c0e6071301 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -15,7 +15,6 @@
#include <stdint.h>
#include <cf9_reset.h>
-#include <delay.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <cpu/x86/lapic.h>
@@ -246,10 +245,8 @@ void mainboard_romstage_entry(void)
enable_lapic();
- /* Force PCIRST# */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
- udelay(200 * 1000);
- pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
+ /* Force PCIRST# to conventional PCI slot and Firewire. */
+ ich7_p2p_secondary_reset();
ich7_enable_lpc();
early_superio_config_w83627thg();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 93b24a0a47..7949b697b7 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -17,7 +17,6 @@
#include <stdint.h>
#include <arch/io.h>
#include <cf9_reset.h>
-#include <delay.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@@ -209,10 +208,8 @@ void mainboard_romstage_entry(void)
enable_lapic();
- /* Force PCIRST# */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
- udelay(200 * 1000);
- pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
+ /* Force PCIRST# to cardbus add-on. */
+ ich7_p2p_secondary_reset();
ich7_enable_lpc();
early_superio_config();