mb/*/*: use ACPIMMIO common block wherever possible

TEST=boot PC Engines apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

37 files changed, 663 insertions, 746 deletions

diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c
index a3c568f820..21d0476204 100644
--- a/src/mainboard/amd/bettong/boardid.c
+++ b/src/mainboard/amd/bettong/boardid.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/mmio.h>
 #include <southbridge/amd/common/amd_defs.h>
 #include <boardid.h>
@@ -30,17 +31,15 @@
  */
 uint32_t board_id(void)
 {
-	void *gpiommioaddr;
 	u8  value = 0;
 	u8  boardrev = 0;
 	char boardid;
 
-	gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500;
-	value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */
+	value = gpio0_read8((7 << 2) + 2); /* agpio7: board_id2 */
 	boardrev = value & 1;
-	value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */
+	value = gpio0_read8((6 << 2) + 2); /* agpio6: board_id1 */
 	boardrev |= (value & 1) << 1;
-	value = read8(gpiommioaddr + (5 << 2) + 2); /* agpio5: board_id0 */
+	value = gpio0_read8((5 << 2) + 2); /* agpio5: board_id0 */
 	boardrev |= (value & 1) << 2;
 
 	boardid = 'A' + boardrev;
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index a3ad3a16e9..77250c2259 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <arch/cpu.h>
@@ -34,8 +35,7 @@ static void romstage_main_template(void)
 	 *  the SoC BKDGs.  Without this setting, there is no serial
 	 *  output.
 	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
+	pm_io_write8(0xd2, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -47,7 +47,5 @@ static void romstage_main_template(void)
 
 void agesa_postcar(struct sysinfo *cb)
 {
-	/* After AMD_INIT_ENV -> move to ramstage ? */
-	outb(0xEA, 0xCD6);
-	outb(0x1, 0xcd7);
+	pm_io_write8(0xea, 1);
 }
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index b6267a69bb..0ae9f28f98 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -46,76 +47,68 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 	UINT32            AcpiMmioAddr;
 	UINT32            GpioMmioAddr;
 	UINT8             Data8;
-	UINT16            Data16;
 	UINT8             TempData8;
 
 	FcnData = Data;
 	MemData = ConfigPtr;
 
 	Status  = AGESA_SUCCESS;
-	/* Get SB MMIO Base (AcpiMmioAddr) */
-	WriteIo8 (0xCD6, 0x27);
-	Data8   = ReadIo8(0xCD7);
-	Data16  = Data8 << 8;
-	WriteIo8 (0xCD6, 0x26);
-	Data8   = ReadIo8(0xCD7);
-	Data16  |= Data8;
-	AcpiMmioAddr = (UINT32)Data16 << 16;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 
 	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
 	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
 	Data8 |= BIT2+BIT3;
 	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
 	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
 	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
 	Data8 |= BIT2+BIT3;
 	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
 	switch (MemData->ParameterListPtr->DDR3Voltage) {
-		case VOLT1_35:
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-			Data8 |= (UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-			break;
-		case VOLT1_25:
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-			break;
-		case VOLT1_5:
-		default:
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-			Data8 |= (UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	case VOLT1_35:
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
 	}
 	return Status;
 }
@@ -130,70 +123,67 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	UINT32  GpioMmioAddr;
 	UINT32  AcpiMmioAddr;
 	UINT8   Data8;
-	UINT16  Data16;
 
 	FcnData   = Data;
 	ResetInfo = ConfigPtr;
-	// Get SB800 MMIO Base (AcpiMmioAddr)
-	WriteIo8(0xCD6, 0x27);
-	Data8 = ReadIo8(0xCD7);
-	Data16 = Data8 << 8;
-	WriteIo8(0xCD6, 0x26);
-	Data8 = ReadIo8(0xCD7);
-	Data16 |= Data8;
-	AcpiMmioAddr = (UINT32)Data16 << 16;
-	Status = AGESA_UNSUPPORTED;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-	switch (ResetInfo->ResetId)
-	{
-		case 4:
-			switch (ResetInfo->ResetControl) {
-				case AssertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-					Data8 &= ~(UINT8)BIT6;
-					Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-					Status = AGESA_SUCCESS;
-					break;
-				case DeassertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-					Data8 |= BIT6;
-					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-					Status = AGESA_SUCCESS;
-					break;
-			}
+	Status = AGESA_UNSUPPORTED;
+	switch (ResetInfo->ResetId) {
+	case 4:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 &= ~(UINT8)BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 |= BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
 			break;
-		case 6:
-			switch (ResetInfo->ResetControl) {
-				case AssertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-					Data8 &= ~(UINT8)BIT6;
-					Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-					Status = AGESA_SUCCESS;
-					break;
-				case DeassertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-					Data8 |= BIT6;
-					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-					Status = AGESA_SUCCESS;
-					break;
-			}
+		}
+		break;
+	case 6:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 &= ~(UINT8)BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
 			break;
-		case 7:
-			switch (ResetInfo->ResetControl) {
-				case AssertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-					Data8 &= ~(UINT8)BIT6;
-					Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-					Status = AGESA_SUCCESS;
-					break;
-				case DeassertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-					Data8 |= BIT6;
-					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-					Status = AGESA_SUCCESS;
-					break;
-			}
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 |= BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
 			break;
+		}
+		break;
+	case 7:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 &= ~(UINT8)BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 |= BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
 	}
-	return  Status;
+	return Status;
 }
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 83fe394be7..47a267b323 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -16,7 +16,6 @@
 #include <amdblocks/acpimmio.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>	/* Platform Specific Definitions */
 
 static void init_gpios(void)
 {
@@ -34,16 +33,15 @@ static void init_gpios(void)
 	/* Multi-function pins switch to GPIO0-35, these pins are shared with
 	 * PCI pins, make sure Hudson PCI device is disabled.
 	 */
-	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
 
 	/* select IOMux to function1/2, corresponds to GPIO */
-	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
-	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
-
+	iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
+	iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
 
 	/* output low */
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
+	gpio_100_write8(0x20, 0x48);
+	gpio_100_write8(0x32, 0x48);
 }
 
 
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index a22b247f27..66188bdc1c 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <arch/cpu.h>
@@ -28,25 +29,8 @@
 
 static void romstage_main_template(void)
 {
-	u32 val;
-
-	/*
-	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  This following register setting has been
-	 *  replicated in every reference design since Parmer, so it is
-	 *  believed to be required even though it is not documented in
-	 *  the SoC BKDGs.  Without this setting, there is no serial
-	 *  output.
-	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
-
-	hudson_lpc_decode();
-
-	outb(0x24, 0xCD6);
-	outb(0x01, 0xCD7);
-	*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
-	*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
+	misc_write32(0x28, misc_read32(0x28) | (1 << 18)); /* 24Mhz */
+	misc_write32(0x40, misc_read32(0x40) & (~(1 << 2))); /* 24Mhz */
 
 	if (!cpu_init_detectedx) {
 		post_code(0x30);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 122bb19e3d..dfe7c49f9f 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
@@ -30,12 +31,10 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	 *  even though the register is not documented in the Kabini BKDG.
 	 *  Otherwise the serial output is bad code.
 	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
+	pm_io_write8(0xd2, 0);
 
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
-	outb(0xea, 0xcd6);
-	outb(0x1, 0xcd7);
+	pm_io_write8(0xea, 1);
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 3dd7d531eb..4d7db013ee 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <arch/cpu.h>
@@ -34,8 +35,7 @@ static void romstage_main_template(void)
 	 *  the SoC BKDGs.  Without this setting, there is no serial
 	 *  output.
 	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
+	pm_io_write8(0xd2, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -64,6 +64,5 @@ static void romstage_main_template(void)
 void agesa_postcar(struct sysinfo *cb)
 {
 	/* After AMD_INIT_ENV -> move to ramstage ? */
-	outb(0xEA, 0xCD6);
-	outb(0x1, 0xcd7);
+	pm_io_write8(0xea, 1);
 }
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 60ce3ee3a5..23a0e9f1e6 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 #include <stdlib.h>
@@ -60,11 +61,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	FcnData = Data;
 	ResetInfo = ConfigPtr;
 	// Get SB800 MMIO Base (AcpiMmioAddr)
-	WriteIo8(0xCD6, 0x27);
-	Data8 = ReadIo8(0xCD7);
+	Data8 = pm_io_read8(0x27);
 	Data16 = Data8 << 8;
-	WriteIo8(0xCD6, 0x26);
-	Data8 = ReadIo8(0xCD7);
+	Data8 = pm_io_read8(0x26);
 	Data16 |= Data8;
 	AcpiMmioAddr = (UINT32)Data16 << 16;
 	Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 0e89ffde05..6ca8a80771 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -126,12 +126,11 @@ static void mainboard_enable(struct device *dev)
 
 	/* enable GPP CLK0 thru CLK1 */
 	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
-	write8(misc_mem_clk_cntrl + 1, 0x00);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(0, 0xff);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index ecb7e1cfd6..45a40b497b 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -37,166 +38,151 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
+	AGESA_STATUS      Status;
+	UINTN             FcnData;
+	MEM_DATA_STRUCT   *MemData;
+	UINT32            AcpiMmioAddr;
+	UINT32            GpioMmioAddr;
+	UINT8             Data8;
+	UINT8             TempData8;
 
-  FcnData = Data;
-  MemData = ConfigPtr;
+	FcnData = Data;
+	MemData = ConfigPtr;
 
-  Status  = AGESA_SUCCESS;
-  /* Get SB MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8 << 8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_SUCCESS;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  return Status;
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_35:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	return Status;
 }
 
 /* PCIE slot reset control */
 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
-  UINTN                 FcnData;
-  PCIe_SLOT_RESET_INFO  *ResetInfo;
+	AGESA_STATUS           Status;
+	UINTN                  FcnData;
+	PCIe_SLOT_RESET_INFO   *ResetInfo;
+	UINT32                 GpioMmioAddr;
+	UINT32                 AcpiMmioAddr;
+	UINT8                  Data8;
 
-  UINT32  GpioMmioAddr;
-  UINT32  AcpiMmioAddr;
-  UINT8   Data8;
-  UINT16  Data16;
-
-  FcnData   = Data;
-  ResetInfo = ConfigPtr;
-  // Get SB800 MMIO Base (AcpiMmioAddr)
-  WriteIo8(0xCD6, 0x27);
-  Data8 = ReadIo8(0xCD7);
-  Data16 = Data8 << 8;
-  WriteIo8(0xCD6, 0x26);
-  Data8 = ReadIo8(0xCD7);
-  Data16 |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  Status = AGESA_UNSUPPORTED;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  switch (ResetInfo->ResetId)
-  {
-  case 4:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 6:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 &= ~(UINT8)BIT6;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 7:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 &= ~(UINT8)BIT6;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 |= BIT6;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  }
-  return  Status;
+	FcnData = Data;
+	ResetInfo = ConfigPtr;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_UNSUPPORTED;
+	switch (ResetInfo->ResetId) {
+	case 4:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 &= ~(UINT8)BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 |= BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	case 6:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 &= ~(UINT8)BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 |= BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	case 7:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 &= ~(UINT8)BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 |= BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	}
+	return Status;
 }
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index 9b041e0111..d9e4c5ff1a 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -17,7 +17,6 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>	/* Platform Specific Definitions */
 
 /**
  * Southstation using SB GPIO 17/18 to control the Red/Green LED
@@ -25,26 +24,21 @@
  */
 static void southstation_led_init(void)
 {
-#define GPIO_FUNCTION	2  //GPIO function
-#define SB_GPIO_REG17	17 //Red  Light
-#define SB_GPIO_REG18	18 //Green Light
-
 	/* multi-function pins switch to GPIO0-35 */
-	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
 
 	/* select IOMux to function2, corresponds to GPIO */
-	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
-	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
+	iomux_write8(0x11, (iomux_read8(0x11) & 0xfc) | 2);
+	iomux_write8(0x12, (iomux_read8(0x12) & 0xfc) | 2);
 
 	/* Lighting test */
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
+	gpio_100_write8(0x11, 0x08); //output high
+	gpio_100_write8(0x12, 0x08);
 	mdelay(100);
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
+	gpio_100_write8(0x11, 0x48); //output low
+	gpio_100_write8(0x12, 0x48);
 }
 
-
 /**********************************************
  * Enable the dedicated functions of the board.
  **********************************************/
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 0a2821ba60..dff516ca3a 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -47,9 +48,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	post_code(0x31);
 	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
-	outb(0x24, 0xcd6);
-	outb(0x1, 0xcd7);
-	outb(0xea, 0xcd6);
-	outb(0x1, 0xcd7);
+	pm_io_write8(0x24, 1);
+	pm_io_write8(0xea, 1);
 	gpio_100_write8(0x1, 0x98);
 }
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index ecb7e1cfd6..c701a7e4e2 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -37,166 +38,151 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
+	AGESA_STATUS       Status;
+	UINTN              FcnData;
+	MEM_DATA_STRUCT    *MemData;
+	UINT32             AcpiMmioAddr;
+	UINT32             GpioMmioAddr;
+	UINT8              Data8;
+	UINT8              TempData8;
 
-  FcnData = Data;
-  MemData = ConfigPtr;
+	FcnData = Data;
+	MemData = ConfigPtr;
 
-  Status  = AGESA_SUCCESS;
-  /* Get SB MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8 << 8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_SUCCESS;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  return Status;
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_35:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	return Status;
 }
 
 /* PCIE slot reset control */
 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
-  UINTN                 FcnData;
-  PCIe_SLOT_RESET_INFO  *ResetInfo;
+	AGESA_STATUS            Status;
+	UINTN                   FcnData;
+	PCIe_SLOT_RESET_INFO    *ResetInfo;
+	UINT32                  GpioMmioAddr;
+	UINT32                  AcpiMmioAddr;
+	UINT8                   Data8;
 
-  UINT32  GpioMmioAddr;
-  UINT32  AcpiMmioAddr;
-  UINT8   Data8;
-  UINT16  Data16;
-
-  FcnData   = Data;
-  ResetInfo = ConfigPtr;
-  // Get SB800 MMIO Base (AcpiMmioAddr)
-  WriteIo8(0xCD6, 0x27);
-  Data8 = ReadIo8(0xCD7);
-  Data16 = Data8 << 8;
-  WriteIo8(0xCD6, 0x26);
-  Data8 = ReadIo8(0xCD7);
-  Data16 |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  Status = AGESA_UNSUPPORTED;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  switch (ResetInfo->ResetId)
-  {
-  case 4:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 6:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 &= ~(UINT8)BIT6;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 7:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 &= ~(UINT8)BIT6;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 |= BIT6;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  }
-  return  Status;
+	FcnData = Data;
+	ResetInfo = ConfigPtr;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_UNSUPPORTED;
+	switch (ResetInfo->ResetId) {
+	case 4:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 &= ~(UINT8)BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 |= BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	case 6:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 &= ~(UINT8)BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 |= BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	case 7:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 &= ~(UINT8)BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 |= BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	}
+	return Status;
 }
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index 5d7211c3e6..c9ecad746a 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 
@@ -34,88 +35,81 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
+	AGESA_STATUS       Status;
+	UINTN              FcnData;
+	MEM_DATA_STRUCT    *MemData;
+	UINT32             AcpiMmioAddr;
+	UINT32             GpioMmioAddr;
+	UINT8              Data8;
+	UINT8              TempData8;
 
-  FcnData = Data;
-  MemData = ConfigPtr;
+	FcnData = Data;
+	MemData = ConfigPtr;
 
-  Status  = AGESA_SUCCESS;
-  /* Get SB800 MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8 << 8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_SUCCESS;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
-  /* this seems to be just copy-pasted from the AMD reference boards and needs
-   * some investigation
-   */
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  // disable memory clear for boot time reduction
-  MemData->ParameterListPtr->EnableMemClr = FALSE;
-  return Status;
+	/*
+	 * this seems to be just copy-pasted from the AMD reference boards and
+	 * needs some investigation
+	 */
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_35:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	/* disable memory clear for boot time reduction */
+	MemData->ParameterListPtr->EnableMemClr = FALSE;
+	return Status;
 }
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index e2f4f2b259..96744a39bd 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -26,19 +26,17 @@ static void mainboard_enable(struct device *dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-	/* Power off unused clock pins of GPP PCIe devices */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	/*
+	/* Power off unused clock pins of GPP PCIe devices
 	 * GPP CLK0 connected to unpopulated mini PCIe slot
 	 * GPP CLK1 connected to ethernet chip
 	 */
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
+	misc_write8(0, 0xff);
 	/* GPP CLK2 connected to the external USB3 controller */
-	write8(misc_mem_clk_cntrl + 1, 0x0F);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
+	misc_write8(1, 0x0f);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
 	/* SLT_GFX_CLK connected to PCIe slot */
-	write8(misc_mem_clk_cntrl + 4, 0xF0);
+	misc_write8(4, 0xf0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/asrock/imb-a180/bootblock.c b/src/mainboard/asrock/imb-a180/bootblock.c
index eb5641ff5e..e87dc21f87 100644
--- a/src/mainboard/asrock/imb-a180/bootblock.c
+++ b/src/mainboard/asrock/imb-a180/bootblock.c
@@ -21,20 +21,14 @@
 
 void bootblock_mainboard_early_init(void)
 {
-	u32 reg32;
-
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
 	pm_write8(0xea, 0x1);
 
 	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
-	reg32 = misc_read32(0x28);
-	reg32 &= 0xfff8ffff;
-	misc_write32(0x28, reg32);
+	misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
 
 	/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
-	reg32 = misc_read32(0x40);
-	reg32 &= 0xffffbffb;
-	misc_write32(0x40, reg32);
+	misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
 
 	/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c
index ddbf2aa548..2a3aabd7e9 100644
--- a/src/mainboard/asus/am1i-a/bootblock.c
+++ b/src/mainboard/asus/am1i-a/bootblock.c
@@ -113,7 +113,7 @@ static void ite_gpio_conf(pnp_devfn_t dev)
 
 void bootblock_mainboard_early_init(void)
 {
-	volatile u32 i, val;
+	u32 val, i;
 
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
 	pm_write8(0xea, 0x1);
diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c
index 0472877dc0..3d980a663d 100644
--- a/src/mainboard/asus/f2a85-m/bootblock.c
+++ b/src/mainboard/asus/f2a85-m/bootblock.c
@@ -32,9 +32,7 @@ static void sbxxx_enable_48mhzout(void)
 	reg32 |= 0x00100000;
 	misc_write32(0x28, reg32);
 
-	reg32 = misc_read32(0x40);
-	reg32 &= ~0x80u;
-	misc_write32(0x40, reg32);
+	misc_write32(0x40, misc_read32(0x40) & (~0x80u));
 }
 
 static void superio_init_m(void)
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 3aa29c8ce3..5b7494d9ee 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <arch/io.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/smbus.h>
@@ -26,10 +27,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	post_code(0x30);
 
 	/* turn on secondary smbus at b20 */
-	outb(0x28, 0xcd6);
-	byte = inb(0xcd7);
-	byte |= 1;
-	outb(byte, 0xcd7);
+	pm_write8(0x28, pm_read8(0x28) | 1);
 
 	/* set DDR3 voltage */
 	byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 505de38d9e..c1b96f1273 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_ops.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
@@ -29,8 +30,7 @@
 void board_BeforeAgesa(struct sysinfo *cb)
 {
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
-	outb(0xea, 0xcd6);
-	outb(0x1, 0xcd7);
+	pm_io_write(0xea, 1);
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index 9729ffb400..a60e571367 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <arch/cpu.h>
@@ -38,8 +39,7 @@ static void romstage_main_template(void)
 	 *  the SoC BKDGs.  Without this setting, there is no serial
 	 *  output.
 	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
+	pm_io_write8(0xd2, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -52,6 +52,5 @@ static void romstage_main_template(void)
 void agesa_postcar(struct sysinfo *cb)
 {
 	/* After AMD_INIT_ENV -> move to ramstage ? */
-	outb(0xEA, 0xCD6);
-	outb(0x1, 0xcd7);
+	pm_io_write8(0xea, 1);
 }
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c
index 09098f7d8b..5e0cd7c83d 100644
--- a/src/mainboard/biostar/a68n_5200/romstage.c
+++ b/src/mainboard/biostar/a68n_5200/romstage.c
@@ -16,6 +16,7 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
@@ -32,13 +33,11 @@
 static void sbxxx_enable_48mhzout(void)
 {
 	/* most likely programming to 48MHz out signal */
-	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
 	u32 reg32;
 	reg32 = misc_read32(0x28);
 	reg32 &= 0xfff8ffff;
 	misc_write32(0x28, reg32);
 
-	/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
 	reg32 = misc_read32(0x40);
 	reg32 &= 0xffffbffb;
 	misc_write32(0x40, reg32);
@@ -49,8 +48,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	u8 byte;
 
 	/* Enable the AcpiMmio space */
-	outb(0x24, 0xcd6);
-	outb(0x1, 0xcd7);
+	pm_io_write8(0x24, 1);
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c
index 771745e9bd..3eceaa782d 100644
--- a/src/mainboard/biostar/am1ml/bootblock.c
+++ b/src/mainboard/biostar/am1ml/bootblock.c
@@ -61,20 +61,14 @@ static void ite_gpio_conf(pnp_devfn_t dev)
 
 void bootblock_mainboard_early_init(void)
 {
-	u32 reg32;
-
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
 	pm_write8(0xea, 0x1);
 
 	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
-	reg32 = misc_read32(0x28);
-	reg32 &= 0xfff8ffff;
-	misc_write32(0x28, reg32);
+	misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
 
 	/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
-	reg32 = misc_read32(0x40);
-	reg32 &= 0xffffbffb;
-	misc_write32(0x49, reg32);
+	misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
 
 	/* Configure SIO as made under vendor BIOS */
 	ite_evc_conf(ENVC_DEV);
diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
index 6e2eaed80d..01f06bd765 100644
--- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c
+++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 #include <stdlib.h>
@@ -60,11 +61,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	FcnData = Data;
 	ResetInfo = ConfigPtr;
 	// Get SB800 MMIO Base (AcpiMmioAddr)
-	WriteIo8(0xCD6, 0x27);
-	Data8 = ReadIo8(0xCD7);
+	Data8 = pm_io_read8(0x27);
 	Data16=Data8<<8;
-	WriteIo8(0xCD6, 0x26);
-	Data8 = ReadIo8(0xCD7);
+	Data8 = pm_io_read8(0x26);
 	Data16|=Data8;
 	AcpiMmioAddr = (UINT32)Data16 << 16;
 	Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c
index 0e89ffde05..6ca8a80771 100644
--- a/src/mainboard/elmex/pcm205400/mainboard.c
+++ b/src/mainboard/elmex/pcm205400/mainboard.c
@@ -126,12 +126,11 @@ static void mainboard_enable(struct device *dev)
 
 	/* enable GPP CLK0 thru CLK1 */
 	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
-	write8(misc_mem_clk_cntrl + 1, 0x00);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(0, 0xff);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c
index b65f56b074..63d94530e9 100644
--- a/src/mainboard/gizmosphere/gizmo/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo/mainboard.c
@@ -14,12 +14,12 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <device/mmio.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 
 /**********************************************
  * Enable the dedicated functions of the board.
@@ -30,18 +30,17 @@ static void mainboard_enable(struct device *dev)
 
 	/* enable GPP CLK0 thru CLK1 */
 	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
-	write8(misc_mem_clk_cntrl + 1, 0x00);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(0, 0xFF);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/*
 	 * Force the onboard SATA port to GEN2 speed.
 	 * The offboard SATA port can remain at GEN3.
 	 */
-	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+	pm_write8(0xda, (pm_read8(0xda) & 0xfb) | 0x04);
 }
 
 static void mainboard_final(void *chip_info)
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 4676199b47..6312270712 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <northbridge/amd/agesa/state_machine.h>
@@ -29,21 +30,5 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	 *  even though the register is not documented in the Kabini BKDG.
 	 *  Otherwise the serial output is bad code.
 	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
+	pm_io_write8(0xd2, 0);
 }
-
-#if 0
-	/* LPC clock? Should happen before enable_serial. */
-
-	/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
-	int i;
-	for(i = 0; i < 200000; i++)
-		val = inb(0xcd6);
-#endif
-
-#if 0
-	/* Was before copy_and_run. */
-	outb(0xEA, 0xCD6);
-	outb(0x1, 0xcd7);
-#endif
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 079bd7b786..5092e1772f 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <northbridge/amd/agesa/state_machine.h>
@@ -26,7 +27,7 @@
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
-	u32 reg32;
+	u32 t32;
 
 	/* For serial port option, plug-in card on LPC. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -37,32 +38,21 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	 *  even though the register is not documented in the Kabini BKDG.
 	 *  Otherwise the serial output is bad code.
 	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
-
+	pm_io_write8(0xd2, 0);
 
 	/* Enable the AcpiMmio space */
-	outb(0x24, 0xcd6);
-	outb(0x01, 0xcd7);
+	pm_io_write8(0x24, 1);
 
 	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
 	/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
-	reg32 = misc_read32(0x28);
-	reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
-	reg32 |= 0x00010000; // Set bit 16 for 25MHz
-	misc_write32(0x28, reg32);
+	t32 = misc_read32(0x28);
+	t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
+	t32 |= 0x00010000; // Set bit 16 for 25MHz
+	misc_write(0x28, t32);
 
 	/* Enable Auxiliary OSCOUT1/OSCOUT2 */
-	reg32 = misc_read32(0x40;
-	reg32 &= 0xffffff7b; // clear 2, 7
-	misc_write32(0x40, reg32);
+	t32 = misc_write32(0x40, misc_read32(0x40) & 0xffffff7b);
 
 	nct5104d_enable_uartd(SERIAL_DEV);
 	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }
-
-#if 0
-	/* Was before copy_and_run. */
-	outb(0xEA, 0xCD6);
-	outb(0x1, 0xcd7);
-#endif
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 86999fbab4..c2227ae935 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -17,6 +17,7 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <vendorcode/amd/cimx/sb800/SB800.h>
 #include <stdint.h>
 #include <stdlib.h>
@@ -63,11 +64,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	FcnData = Data;
 	ResetInfo = ConfigPtr;
 	/* Get SB800 MMIO Base (AcpiMmioAddr) */
-	WriteIo8(0xCD6, 0x27);
-	Data8 = ReadIo8(0xCD7);
+	Data8 = pm_io_read8(0x27);
 	Data16 = Data8 << 8;
-	WriteIo8(0xCD6, 0x26);
-	Data8 = ReadIo8(0xCD7);
+	Data8 = pm_io_read8(0x26);
 	Data16 |= Data8;
 	AcpiMmioAddr = (uint32_t)Data16 << 16;
 	Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index 0a12c3f66a..cbf75a49ce 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -128,12 +128,11 @@ static void mainboard_enable(struct device *dev)
 
 	/* enable GPP CLK0 thru CLK3 (interleaved) */
 	/* disable GPP CLK4 thru SLT_GFX_CLK */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
-	write8(misc_mem_clk_cntrl + 1, 0xFF);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(0, 0xff);
+	misc_write8(1, 0xff);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index 6ad5234d81..9e3eab7a6c 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -59,32 +59,41 @@ static const u16 sio_init_table[] = { // hi = offset, lo = value
 
 static void init(struct device *dev)
 {
-	volatile u8 *spi_base;	// base addr of Hudson's SPI host controller
+	volatile u8 *spi_base;	/* base addr of Hudson's SPI host controller */
 	int i;
 	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
 
 	/* Init Hudson GPIOs. */
 	printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
-	FCH_IOMUX(50) = 2;    // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
-	FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
-	FCH_IOMUX(197) = 2;    // GPIO197: BIOS_DEFAULTS# = input (int. PU)
-	FCH_IOMUX(56) = 1;    // GPIO58-56: REV_ID2-0
-	FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
-	FCH_IOMUX(57) = 1;
-	FCH_GPIO (57) = 0x28;
-	FCH_IOMUX(58) = 1;
-	FCH_GPIO (58) = 0x28;
-	FCH_IOMUX(96) = 1;    // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
-	FCH_IOMUX(52) = 1;    // GPIO52,61,62,187-192 free to use on X2 connector
-	FCH_IOMUX(61) = 2;    // default to inputs with int. PU
-	FCH_IOMUX(62) = 2;
-	FCH_IOMUX(187) = 2;
-	FCH_IOMUX(188) = 2;
-	FCH_IOMUX(189) = 1;
-	FCH_IOMUX(190) = 1;
-	FCH_IOMUX(191) = 1;
-	FCH_IOMUX(192) = 1;
-	if (!fch_gpio_state(197)) // just in case anyone cares
+	/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
+	iomux_write8(50, 2);
+	/* output set to 1 as it's never needed */
+	iomux_write8(50, 0xc0);
+	/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
+	iomux_write8(197, 2);
+	/* GPIO58-56: REV_ID2-0 */
+	iomux_write8(56, 1);
+	/* inputs, disable int. pull-ups */
+	gpio_100_write8(56, 0x28);
+	iomux_write8(57, 1);
+	gpio_100_write8(57, 0x28);
+	iomux_write8(58, 1);
+	gpio_100_write8(58, 0x28);
+	/* "Gpio96": GEVENT0# signal on X2 connector (int. PU) */
+	iomux_write8(96, 1);
+	/* GPIO52,61,62,187-192 free to use on X2 connector */
+	iomux_write8(52, 1);
+	/* default to inputs with int. PU */
+	iomux_write8(61, 2);
+	iomux_write8(62, 2);
+	iomux_write8(187, 2);
+	iomux_write8(188, 2);
+	iomux_write8(189, 1);
+	iomux_write8(190, 1);
+	iomux_write8(191, 1);
+	iomux_write8(192, 1);
+	/* just in case anyone cares */
+	if (!fch_gpio_state(197))
 		printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
 	printk(BIOS_INFO, "Board revision ID: %u\n",
 	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
@@ -99,9 +108,11 @@ static void init(struct device *dev)
 	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
 	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
 							   0xA0) & 0xFFFFFFE0);
-	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
+	/* NormSpeed in SPI_Cntrl1 register */
+	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
 
-	/* Notify the SMC we're alive and kicking, or after a while it will
+	/*
+	 * Notify the SMC we're alive and kicking, or after a while it will
 	 * effect a power cycle and switch to the alternate BIOS chip.
 	 * Should be done as late as possible.
 	 * Failure here does not matter if watchdog was already disabled,
@@ -122,12 +133,11 @@ static void mainboard_enable(struct device *dev)
 
 	/* enable GPP CLK0 */
 	/* disable GPP CLK1 thru SLT_GFX_CLK */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	write8(misc_mem_clk_cntrl + 0, 0x0F);
-	write8(misc_mem_clk_cntrl + 1, 0x00);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(0, 0x0f);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index 1c9c5a6b91..158613fcac 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -27,36 +27,52 @@
 
 static void init(struct device *dev)
 {
-	volatile u8 *spi_base;	// base addr of Hudson's SPI host controller
+	volatile u8 *spi_base;	/* base addr of Hudson's SPI host controller */
 	printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
 
 	/* Init Hudson GPIOs. */
 	printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
-	FCH_IOMUX(50) = 2;    // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
-	FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
-	FCH_IOMUX(197) = 2;    // GPIO197: BIOS_DEFAULTS#
-	FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
-	FCH_IOMUX(56) = 1;    // GPIO58-56: REV_ID2-0
-	FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
-	FCH_IOMUX(57) = 1;
-	FCH_GPIO (57) = 0x28;
-	FCH_IOMUX(58) = 1;
-	FCH_GPIO (58) = 0x28;
-	FCH_IOMUX(187) = 2;    // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
-	FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
-	FCH_IOMUX(188) = 2;
-	FCH_GPIO (188) = 0x08;
-	FCH_IOMUX(166) = 2;
-	FCH_GPIO (166) = 0x08;
-	// needed to make GPO160 work (Hudson Register Reference section 2.3.6.1)
-	FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01;
-	FCH_IOMUX(160) = 1;
-	FCH_GPIO (160) = 0x08;
-	FCH_IOMUX(189) = 1;    // GPIO189-192: GPI0-3 on COM Express connector
-	FCH_IOMUX(190) = 1;    // default to inputs with int. PU
-	FCH_IOMUX(191) = 1;
-	FCH_IOMUX(192) = 1;
-	if (!fch_gpio_state(197)) // just in case anyone cares
+	/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
+	iomux_write8(50, 2);
+	/* output set to 1 as it's never needed */
+	iomux_write8(50, 0xc0);
+	/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
+	iomux_write8(197, 2);
+	/* input, disable int. pull-up */
+	gpio_100_write8(197, 0x28);
+	/* GPIO58-56: REV_ID2-0 */
+	iomux_write8(56, 1);
+	/* inputs, disable int. pull-ups */
+	gpio_100_write8(56, 0x28);
+	iomux_write8(57, 1);
+	gpio_100_write8(57, 0x28);
+	iomux_write8(58, 1);
+	gpio_100_write8(58, 0x28);
+	/* GPIO187,188,166,GPO160: GPO0-3 on COM Express connector */
+	iomux_write8(187, 2);
+	/* outputs, disable PUs, default to 0 */
+	gpio_100_write8(187, 0x08);
+	iomux_write8(188, 2);
+	gpio_100_write8(188, 0x08);
+	iomux_write8(166, 2);
+	gpio_100_write8(166, 0x08);
+	/*
+	 * needed to make GPO160 work (Hudson Register Reference
+	 * section 2.3.6.1)
+	 */
+	pm_write8(0xdc, pm_read8(0xdc) & (~0x80));
+	pm_write8(0xe6, (pm_read8(0xe6) & (~0x02)) | 1);
+	iomux_write8(160, 1);
+	gpio_100_write8(160, 0x08);
+	/* GPIO189-192: GPI0-3 on COM Express connector */
+	iomux_write8(189, 1);
+	/* default to inputs with int. PU */
+	iomux_write8(190, 1);
+	iomux_write8(191, 1);
+	iomux_write8(192, 1);
+
+	/* just in case anyone cares */
+	if (!fch_gpio_state(197))
 		printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
 	printk(BIOS_INFO, "Board revision ID: %u\n",
 	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
@@ -64,9 +80,11 @@ static void init(struct device *dev)
 	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
 	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
 							   0xA0) & 0xFFFFFFE0);
-	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
+	/* NormSpeed in SPI_Cntrl1 register */
+	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
 
-	/* Notify the SMC we're alive and kicking, or after a while it will
+	/*
+	 * Notify the SMC we're alive and kicking, or after a while it will
 	 * effect a power cycle and switch to the alternate BIOS chip.
 	 * Should be done as late as possible.
 	 * Failure here does not matter if watchdog was already disabled,
@@ -87,12 +105,11 @@ static void mainboard_enable(struct device *dev)
 
 	/* enable GPP CLK0 thru CLK1 */
 	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
-	write8(misc_mem_clk_cntrl + 1, 0x00);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(0, 0xff);
+	misc_write8(1, 0);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c
index 4e58d5593b..206dc63c9d 100644
--- a/src/mainboard/pcengines/apu1/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.c
@@ -27,25 +27,21 @@ uintptr_t find_gpio_base(void)
 	return base_addr;
 }
 
-void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting)
+void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting)
 {
 	u8 bdata;
-	u8 *memptr;
 
-	memptr = (u8 *)(base_addr + IOMUX_OFFSET + gpio);
-	*memptr = iomux_ftn;
+	iomux_write8(gpio, iomux_ftn);
 
-	memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
-	bdata = *memptr;
+	bdata = gpio_100_read8(gpio);
 	bdata &= 0x07;
 	bdata |= setting; /* set direction and data value */
-	*memptr = bdata;
+	gpio_100_write8(gpio, bdata);
 }
 
-u8 read_gpio(uintptr_t base_addr, u32 gpio)
+u8 read_gpio(uintptr_t base_addr, u8 gpio)
 {
-	u8 *memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
-	return (*memptr & GPIO_DATA_IN) ? 1 : 0;
+	return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0;
 }
 
 int get_spd_offset(void)
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h
index fce8afe6f0..fb582721d2 100644
--- a/src/mainboard/pcengines/apu1/gpio_ftns.h
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.h
@@ -19,8 +19,8 @@
 #include <stdint.h>
 
 uintptr_t find_gpio_base(void);
-void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting);
-u8 read_gpio(uintptr_t base_addr, u32 gpio);
+void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting);
+u8 read_gpio(uintptr_t base_addr, u8 gpio);
 int get_spd_offset(void);
 
 #define IOMUX_OFFSET    0xD00
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 854fb8ad4d..0528468e5d 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/mmio.h>
@@ -181,17 +182,17 @@ static void mainboard_enable(struct device *dev)
 	config_gpio_mux();
 	config_addon_uart();
 
-	/* Power off unused clock pins of GPP PCIe devices */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	/* GPP CLK0-2 are connected to the 3 ethernet chips
-	 * GPP CLK3-4 are connected to the miniPCIe slots */
-	write8(misc_mem_clk_cntrl + 0, 0x21);
-	write8(misc_mem_clk_cntrl + 1, 0x43);
+	/* Power off unused clock pins of GPP PCIe devices
+	 * GPP CLK0-2 are connected to the 3 ethernet chips
+	 * GPP CLK3-4 are connected to the miniPCIe slots
+	 */
+	misc_write8(0, 0x21);
+	misc_write8(1, 0x43);
 	/* GPP CLK5 is only connected to test pads -> disable */
-	write8(misc_mem_clk_cntrl + 2, 0x05);
+	misc_write8(2, 0x05);
 	/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
-	write8(misc_mem_clk_cntrl + 3, 0x00);
-	write8(misc_mem_clk_cntrl + 4, 0x00);
+	misc_write8(3, 0);
+	misc_write8(4, 0);
 
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
index 249ecc3494..170acca8d3 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -14,55 +14,75 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
+#include <console/console.h>
 #include <device/mmio.h>
 #include <FchPlatform.h>
 #include "gpio_ftns.h"
 
-void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
+static u32 gpio_read_wrapper(u32 gpio)
+{
+	if (gpio < 0x100)
+		return gpio0_read32(gpio & 0xff);
+	else if (gpio >= 0x100 && gpio < 0x200)
+		return gpio1_read32(gpio & 0xff);
+	else if (gpio >= 0x200 && gpio < 0x300)
+		return gpio2_read32(gpio & 0xff);
+
+	die("Invalid GPIO");
+}
+
+static void gpio_write_wrapper(u32 gpio, u32 setting)
+{
+	if (gpio < 0x100)
+		gpio0_write32(gpio & 0xff, setting);
+	else if (gpio >= 0x100 && gpio < 0x200)
+		gpio1_write32(gpio & 0xff, setting);
+	else if (gpio >= 0x200 && gpio < 0x300)
+		gpio2_write32(gpio & 0xff, setting);
+}
+
+void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
 {
 	u32 bdata;
 
-	bdata = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET
-		+ gpio));
+	bdata =  gpio_read_wrapper(gpio);
 	/* out the data value to prevent glitches */
 	bdata |= (setting & GPIO_OUTPUT_ENABLE);
-	write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata);
+	gpio_write_wrapper(gpio, bdata);
 
 	/* set direction and data value */
 	bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE
 			| GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE));
-	write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata);
+	gpio_write_wrapper(gpio, bdata);
 
-	write8((volatile void *)(ACPI_MMIO_BASE + IOMUX_OFFSET + iomux_gpio),
-			iomux_ftn & 0x3);
+	iomux_write8(iomux_gpio, iomux_ftn & 0x3);
 }
 
 u8 read_gpio(u32 gpio)
 {
-	u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET
-			+ gpio));
-
-	return (status & GPIO_PIN_STS) ? 1 : 0;
+	return (gpio_read_wrapper(gpio) & GPIO_PIN_STS) ? 1 : 0;
 }
 
 void write_gpio(u32 gpio, u8 value)
 {
-	u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET
-			+ gpio));
+	u32 status = gpio_read_wrapper(gpio);
 	status &= ~GPIO_OUTPUT_VALUE;
 	status |= (value > 0) ? GPIO_OUTPUT_VALUE : 0;
-	write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), status);
+	gpio_write_wrapper(gpio, status);
 }
 
 int get_spd_offset(void)
 {
 	u8 index = 0;
-	/* One SPD file contains all 4 options, determine which index to
+	/*
+	 * One SPD file contains all 4 options, determine which index to
 	 * read here, then call into the standard routines.
 	 */
-	u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE);
-	if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0;
-	if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1;
+	if (gpio1_read8(0x02) & BIT0)
+		index |= BIT0;
+	if (gpio1_read8(0x06) & BIT0)
+		index |= BIT1;
 
 	return index;
 }
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
index 24d6a7f772..49169be121 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.h
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -16,7 +16,7 @@
 #ifndef GPIO_FTNS_H
 #define GPIO_FTNS_H
 
-void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
 u8 read_gpio(u32 gpio);
 void write_gpio(u32 gpio, u8 value);
 int get_spd_offset(void);