diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-09-19 14:15:10 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-03 23:59:52 +0000 |
| commit | af36f1d5259884d89e1523fc251393846683361c (patch) | |
| tree | f0de707901be442decbbb5bdc85373a48f6bb42c /src/mainboard | |
| parent | 17034d6f63e214056f90e2d2001deca2f9753316 (diff) | |
| download | coreboot-af36f1d5259884d89e1523fc251393846683361c.tar.xz | |
mainboard/intel/cannonlake_rvp: enable SD card
Set SCS SD enable FSP parameter and set card detect
gpio information.
Change-Id: Ic99466c0d2d59070418d765442ff6d217023803b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 23bdbc8f33..2f472e249b 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -10,6 +10,7 @@ chip soc/intel/cannonlake register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" @@ -70,6 +71,9 @@ chip soc/intel/cannonlake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index bdb06e8679..80b4c43943 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -10,6 +10,7 @@ chip soc/intel/cannonlake register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" @@ -68,6 +69,9 @@ chip soc/intel/cannonlake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |