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authorAaron Durbin <adurbin@chromium.org>2016-07-25 21:31:41 -0500
committerDuncan Laurie <dlaurie@chromium.org>2016-07-30 01:36:32 +0200
commitb0f81518b5c17466bc95ebdef292e82c4b76bc88 (patch)
tree7174d0006c9a8450ada5aeb7c6fe6377407e96a6 /src/mainboard
parent212820c8d728c59fa3228ce92bc1d549b232e35a (diff)
downloadcoreboot-b0f81518b5c17466bc95ebdef292e82c4b76bc88.tar.xz
chromeos mainboards: remove chromeos.asl
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/auron/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/auron/chromeos.c10
-rw-r--r--src/mainboard/google/auron/dsdt.asl1
-rw-r--r--src/mainboard/google/auron/mainboard.c2
-rw-r--r--src/mainboard/google/auron_paine/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/auron_paine/chromeos.c10
-rw-r--r--src/mainboard/google/auron_paine/dsdt.asl1
-rw-r--r--src/mainboard/google/auron_paine/mainboard.c2
-rw-r--r--src/mainboard/google/butterfly/acpi/chromeos.asl20
-rw-r--r--src/mainboard/google/butterfly/chromeos.c12
-rw-r--r--src/mainboard/google/butterfly/dsdt.asl1
-rw-r--r--src/mainboard/google/butterfly/mainboard.c2
-rw-r--r--src/mainboard/google/chell/acpi/chromeos.asl23
-rw-r--r--src/mainboard/google/chell/chromeos.c10
-rw-r--r--src/mainboard/google/chell/dsdt.asl1
-rw-r--r--src/mainboard/google/chell/mainboard.c2
-rw-r--r--src/mainboard/google/cyan/acpi/chromeos.asl33
-rw-r--r--src/mainboard/google/cyan/chromeos.c10
-rw-r--r--src/mainboard/google/cyan/dsdt.asl1
-rw-r--r--src/mainboard/google/cyan/mainboard.c2
-rw-r--r--src/mainboard/google/falco/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/falco/chromeos.c11
-rw-r--r--src/mainboard/google/falco/dsdt.asl1
-rw-r--r--src/mainboard/google/falco/mainboard.c2
-rw-r--r--src/mainboard/google/glados/acpi/chromeos.asl23
-rw-r--r--src/mainboard/google/glados/chromeos.c10
-rw-r--r--src/mainboard/google/glados/dsdt.asl1
-rw-r--r--src/mainboard/google/glados/mainboard.c2
-rw-r--r--src/mainboard/google/guado/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/guado/chromeos.c10
-rw-r--r--src/mainboard/google/guado/dsdt.asl1
-rw-r--r--src/mainboard/google/guado/mainboard.c2
-rw-r--r--src/mainboard/google/jecht/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/jecht/chromeos.c10
-rw-r--r--src/mainboard/google/jecht/dsdt.asl1
-rw-r--r--src/mainboard/google/jecht/mainboard.c2
-rw-r--r--src/mainboard/google/lars/acpi/chromeos.asl24
-rw-r--r--src/mainboard/google/lars/chromeos.c10
-rw-r--r--src/mainboard/google/lars/dsdt.asl1
-rw-r--r--src/mainboard/google/lars/mainboard.c2
-rw-r--r--src/mainboard/google/link/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/link/chromeos.c11
-rw-r--r--src/mainboard/google/link/dsdt.asl1
-rw-r--r--src/mainboard/google/link/mainboard.c2
-rw-r--r--src/mainboard/google/ninja/acpi/chromeos.asl31
-rw-r--r--src/mainboard/google/ninja/chromeos.c12
-rw-r--r--src/mainboard/google/ninja/dsdt.asl1
-rw-r--r--src/mainboard/google/ninja/mainboard.c2
-rw-r--r--src/mainboard/google/panther/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/panther/chromeos.c10
-rw-r--r--src/mainboard/google/panther/dsdt.asl1
-rw-r--r--src/mainboard/google/panther/mainboard.c2
-rw-r--r--src/mainboard/google/parrot/acpi/chromeos.asl20
-rw-r--r--src/mainboard/google/parrot/chromeos.c12
-rw-r--r--src/mainboard/google/parrot/dsdt.asl1
-rw-r--r--src/mainboard/google/parrot/mainboard.c2
-rw-r--r--src/mainboard/google/peppy/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/peppy/chromeos.c11
-rw-r--r--src/mainboard/google/peppy/dsdt.asl1
-rw-r--r--src/mainboard/google/peppy/mainboard.c2
-rw-r--r--src/mainboard/google/rambi/acpi/chromeos.asl32
-rw-r--r--src/mainboard/google/rambi/chromeos.c11
-rw-r--r--src/mainboard/google/rambi/dsdt.asl1
-rw-r--r--src/mainboard/google/rambi/mainboard.c2
-rw-r--r--src/mainboard/google/reef/acpi/chromeos.asl23
-rw-r--r--src/mainboard/google/reef/chromeos.c11
-rw-r--r--src/mainboard/google/reef/dsdt.asl1
-rw-r--r--src/mainboard/google/reef/mainboard.c2
-rw-r--r--src/mainboard/google/rikku/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/rikku/chromeos.c10
-rw-r--r--src/mainboard/google/rikku/dsdt.asl1
-rw-r--r--src/mainboard/google/rikku/mainboard.c2
-rw-r--r--src/mainboard/google/samus/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/samus/chromeos.c10
-rw-r--r--src/mainboard/google/samus/dsdt.asl1
-rw-r--r--src/mainboard/google/samus/mainboard.c2
-rw-r--r--src/mainboard/google/stout/acpi/chromeos.asl22
-rw-r--r--src/mainboard/google/stout/chromeos.c12
-rw-r--r--src/mainboard/google/stout/dsdt.asl1
-rw-r--r--src/mainboard/google/stout/mainboard.c2
-rw-r--r--src/mainboard/google/tidus/acpi/chromeos.asl19
-rw-r--r--src/mainboard/google/tidus/chromeos.c10
-rw-r--r--src/mainboard/google/tidus/dsdt.asl1
-rw-r--r--src/mainboard/google/tidus/mainboard.c2
-rw-r--r--src/mainboard/intel/amenia/acpi/chromeos.asl24
-rw-r--r--src/mainboard/intel/amenia/chromeos.c11
-rw-r--r--src/mainboard/intel/amenia/dsdt.asl3
-rw-r--r--src/mainboard/intel/baskingridge/acpi/chromeos.asl20
-rw-r--r--src/mainboard/intel/baskingridge/chromeos.c12
-rw-r--r--src/mainboard/intel/baskingridge/dsdt.asl1
-rw-r--r--src/mainboard/intel/baskingridge/mainboard.c4
-rw-r--r--src/mainboard/intel/emeraldlake2/acpi/chromeos.asl20
-rw-r--r--src/mainboard/intel/emeraldlake2/chromeos.c12
-rw-r--r--src/mainboard/intel/emeraldlake2/dsdt.asl1
-rw-r--r--src/mainboard/intel/emeraldlake2/mainboard.c2
-rw-r--r--src/mainboard/intel/kunimitsu/acpi/chromeos.asl24
-rw-r--r--src/mainboard/intel/kunimitsu/chromeos.c10
-rw-r--r--src/mainboard/intel/kunimitsu/dsdt.asl1
-rw-r--r--src/mainboard/intel/kunimitsu/mainboard.c2
-rw-r--r--src/mainboard/intel/strago/acpi/chromeos.asl33
-rw-r--r--src/mainboard/intel/strago/chromeos.c10
-rw-r--r--src/mainboard/intel/strago/dsdt.asl1
-rw-r--r--src/mainboard/intel/strago/mainboard.c2
-rw-r--r--src/mainboard/intel/wtm2/acpi/chromeos.asl20
-rw-r--r--src/mainboard/intel/wtm2/chromeos.c12
-rw-r--r--src/mainboard/intel/wtm2/dsdt.asl1
-rw-r--r--src/mainboard/intel/wtm2/mainboard.c2
-rw-r--r--src/mainboard/samsung/lumpy/acpi/chromeos.asl20
-rw-r--r--src/mainboard/samsung/lumpy/chromeos.c12
-rw-r--r--src/mainboard/samsung/lumpy/dsdt.asl1
-rw-r--r--src/mainboard/samsung/lumpy/mainboard.c2
-rw-r--r--src/mainboard/samsung/stumpy/acpi/chromeos.asl20
-rw-r--r--src/mainboard/samsung/stumpy/chromeos.c12
-rw-r--r--src/mainboard/samsung/stumpy/dsdt.asl1
-rw-r--r--src/mainboard/samsung/stumpy/mainboard.c2
115 files changed, 369 insertions, 675 deletions
diff --git a/src/mainboard/google/auron/acpi/chromeos.asl b/src/mainboard/google/auron/acpi/chromeos.asl
deleted file mode 100644
index 85b441567c..0000000000
--- a/src/mainboard/google/auron/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
- Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c
index 4447ddcbbb..20685c67d1 100644
--- a/src/mainboard/google/auron/chromeos.c
+++ b/src/mainboard/google/auron/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
index 58c34813ea..531d6a7247 100644
--- a/src/mainboard/google/auron/dsdt.asl
+++ b/src/mainboard/google/auron/dsdt.asl
@@ -47,7 +47,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c
index 7b67cc06aa..188c16d221 100644
--- a/src/mainboard/google/auron/mainboard.c
+++ b/src/mainboard/google/auron/mainboard.c
@@ -28,6 +28,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
@@ -88,6 +89,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/auron_paine/acpi/chromeos.asl b/src/mainboard/google/auron_paine/acpi/chromeos.asl
deleted file mode 100644
index 85b441567c..0000000000
--- a/src/mainboard/google/auron_paine/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
- Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c
index 4447ddcbbb..20685c67d1 100644
--- a/src/mainboard/google/auron_paine/chromeos.c
+++ b/src/mainboard/google/auron_paine/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/auron_paine/dsdt.asl b/src/mainboard/google/auron_paine/dsdt.asl
index 58c34813ea..531d6a7247 100644
--- a/src/mainboard/google/auron_paine/dsdt.asl
+++ b/src/mainboard/google/auron_paine/dsdt.asl
@@ -47,7 +47,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/auron_paine/mainboard.c b/src/mainboard/google/auron_paine/mainboard.c
index a73a4bd298..81ca9cf1bc 100644
--- a/src/mainboard/google/auron_paine/mainboard.c
+++ b/src/mainboard/google/auron_paine/mainboard.c
@@ -28,6 +28,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
@@ -61,6 +62,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
GMA_INT15_PANEL_FIT_CENTERING,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
diff --git a/src/mainboard/google/butterfly/acpi/chromeos.asl b/src/mainboard/google/butterfly/acpi/chromeos.asl
deleted file mode 100644
index a6cf28e309..0000000000
--- a/src/mainboard/google/butterfly/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
- Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
- Package() { 0x003, 0, 6, "PantherPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 69887f5a68..b25d78e684 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -23,6 +23,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/quanta/ene_kb3940q/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#define WP_GPIO 6
@@ -136,3 +137,14 @@ int get_recovery_mode_switch(void)
return ec_rec_mode;
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
index 4b0e7305a0..3e13a41c12 100644
--- a/src/mainboard/google/butterfly/dsdt.asl
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index ac005d8931..2c5170d27d 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -34,6 +34,7 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/quanta/ene_kb3940q/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
static unsigned int search(char *p, char *a, unsigned int lengthp,
unsigned int lengtha)
@@ -276,6 +277,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = butterfly_onboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/chell/acpi/chromeos.asl b/src/mainboard/google/chell/acpi/chromeos.asl
deleted file mode 100644
index 90b1a4fad2..0000000000
--- a/src/mainboard/google/chell/acpi/chromeos.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})
diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c
index f0b3613f55..3ca1872f04 100644
--- a/src/mainboard/google/chell/chromeos.c
+++ b/src/mainboard/google/chell/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/chell/dsdt.asl b/src/mainboard/google/chell/dsdt.asl
index c9e13e7e45..b5a37c68cc 100644
--- a/src/mainboard/google/chell/dsdt.asl
+++ b/src/mainboard/google/chell/dsdt.asl
@@ -45,7 +45,6 @@ DefinitionBlock(
}
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/chell/mainboard.c b/src/mainboard/google/chell/mainboard.c
index 6033e21ab8..bfa79b4df6 100644
--- a/src/mainboard/google/chell/mainboard.c
+++ b/src/mainboard/google/chell/mainboard.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <stdlib.h>
#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(device_t dev)
@@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl
deleted file mode 100644
index 0bb7985c01..0000000000
--- a/src/mainboard/google/cyan/acpi/chromeos.asl
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: We need to encode gpios within the 4 separate banks
- * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
- * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
- */
-
-Name(OIPG, Package() {
- /* No physical recovery button */
- Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
- Package () { 0x0003, 1, 0x10013, "Braswell" },
-})
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
index 757db5feb7..f606d09c7d 100644
--- a/src/mainboard/google/cyan/chromeos.c
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -123,3 +123,13 @@ int get_write_protect_state(void)
return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
& PAD_VAL_HIGH);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl
index b3c970ddb8..cb6d91a5b8 100644
--- a/src/mainboard/google/cyan/dsdt.asl
+++ b/src/mainboard/google/cyan/dsdt.asl
@@ -53,7 +53,6 @@ DefinitionBlock(
#include <soc/intel/common/acpi/wifi.asl>
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c
index 0566c8e2f6..71ba62b13e 100644
--- a/src/mainboard/google/cyan/mainboard.c
+++ b/src/mainboard/google/cyan/mainboard.c
@@ -18,6 +18,7 @@
#include <bootstate.h>
#include <device/device.h>
#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(device_t dev)
@@ -32,6 +33,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
diff --git a/src/mainboard/google/falco/acpi/chromeos.asl b/src/mainboard/google/falco/acpi/chromeos.asl
deleted file mode 100644
index 673985fc25..0000000000
--- a/src/mainboard/google/falco/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
- Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c
index 1659d9cc87..a8cef3279b 100644
--- a/src/mainboard/google/falco/chromeos.c
+++ b/src/mainboard/google/falco/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
@@ -86,3 +87,13 @@ int get_write_protect_state(void)
{
return get_gpio(58);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl
index 1020ae71b5..f4a462757d 100644
--- a/src/mainboard/google/falco/dsdt.asl
+++ b/src/mainboard/google/falco/dsdt.asl
@@ -54,7 +54,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c
index b9ce50eba9..10252d82b1 100644
--- a/src/mainboard/google/falco/mainboard.c
+++ b/src/mainboard/google/falco/mainboard.c
@@ -29,6 +29,7 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
@@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl
deleted file mode 100644
index 90b1a4fad2..0000000000
--- a/src/mainboard/google/glados/acpi/chromeos.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})
diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c
index f0b3613f55..3ca1872f04 100644
--- a/src/mainboard/google/glados/chromeos.c
+++ b/src/mainboard/google/glados/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl
index c9e13e7e45..b5a37c68cc 100644
--- a/src/mainboard/google/glados/dsdt.asl
+++ b/src/mainboard/google/glados/dsdt.asl
@@ -45,7 +45,6 @@ DefinitionBlock(
}
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index d387fef239..855d69d6a1 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <stdlib.h>
#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(device_t dev)
@@ -73,6 +74,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/guado/acpi/chromeos.asl b/src/mainboard/google/guado/acpi/chromeos.asl
deleted file mode 100644
index 492ee6b272..0000000000
--- a/src/mainboard/google/guado/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
- Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/guado/chromeos.c b/src/mainboard/google/guado/chromeos.c
index 13fbfc3dea..710ab48d9e 100644
--- a/src/mainboard/google/guado/chromeos.c
+++ b/src/mainboard/google/guado/chromeos.c
@@ -93,3 +93,13 @@ void save_chromeos_gpios(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
}
#endif
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/guado/dsdt.asl b/src/mainboard/google/guado/dsdt.asl
index e0786940c9..c3d1fc9171 100644
--- a/src/mainboard/google/guado/dsdt.asl
+++ b/src/mainboard/google/guado/dsdt.asl
@@ -46,7 +46,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/guado/mainboard.c b/src/mainboard/google/guado/mainboard.c
index 3287a7e6a2..1d65829add 100644
--- a/src/mainboard/google/guado/mainboard.c
+++ b/src/mainboard/google/guado/mainboard.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
void mainboard_suspend_resume(void)
@@ -35,6 +36,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/jecht/acpi/chromeos.asl b/src/mainboard/google/jecht/acpi/chromeos.asl
deleted file mode 100644
index 492ee6b272..0000000000
--- a/src/mainboard/google/jecht/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
- Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index cc19666d15..c22f942960 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -94,3 +94,13 @@ void save_chromeos_gpios(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
}
#endif
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl
index b434727ec8..3132aab20a 100644
--- a/src/mainboard/google/jecht/dsdt.asl
+++ b/src/mainboard/google/jecht/dsdt.asl
@@ -47,7 +47,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c
index 58c0190b59..cb17797e97 100644
--- a/src/mainboard/google/jecht/mainboard.c
+++ b/src/mainboard/google/jecht/mainboard.c
@@ -30,6 +30,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
void mainboard_suspend_resume(void)
@@ -135,6 +136,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
diff --git a/src/mainboard/google/lars/acpi/chromeos.asl b/src/mainboard/google/lars/acpi/chromeos.asl
deleted file mode 100644
index 4fc5f22984..0000000000
--- a/src/mainboard/google/lars/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})
diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c
index 1e0bd3c093..daa85c69e0 100644
--- a/src/mainboard/google/lars/chromeos.c
+++ b/src/mainboard/google/lars/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl
index c9e13e7e45..b5a37c68cc 100644
--- a/src/mainboard/google/lars/dsdt.asl
+++ b/src/mainboard/google/lars/dsdt.asl
@@ -45,7 +45,6 @@ DefinitionBlock(
}
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c
index 6725f134d3..e0444059bf 100644
--- a/src/mainboard/google/lars/mainboard.c
+++ b/src/mainboard/google/lars/mainboard.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <stdlib.h>
#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(device_t dev)
@@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/link/acpi/chromeos.asl b/src/mainboard/google/link/acpi/chromeos.asl
deleted file mode 100644
index eec650acb2..0000000000
--- a/src/mainboard/google/link/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button
- Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index d07e8514e3..4be31d9fa4 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -22,6 +22,7 @@
#include <southbridge/intel/common/gpio.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -107,3 +108,13 @@ int get_recovery_mode_switch(void)
return !!(ec_events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl
index be6a412486..da4587d2f3 100644
--- a/src/mainboard/google/link/dsdt.asl
+++ b/src/mainboard/google/link/dsdt.asl
@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 922061f6da..53915d2083 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -36,6 +36,7 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
/* placeholder for evenual link post. Not sure what we'll
* do but it will look nice
@@ -199,6 +200,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
diff --git a/src/mainboard/google/ninja/acpi/chromeos.asl b/src/mainboard/google/ninja/acpi/chromeos.asl
deleted file mode 100644
index 814380c763..0000000000
--- a/src/mainboard/google/ninja/acpi/chromeos.asl
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: On Bay Trail we need to encode gpios within the 3 separate banks
- * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
- * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0x2008, "BayTrail" }, // recovery
- Package () { 0x0003, 1, 0x2006, "BayTrail" }, // firmware write protect
-})
diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c
index baafb6f798..1213266d3f 100644
--- a/src/mainboard/google/ninja/chromeos.c
+++ b/src/mainboard/google/ninja/chromeos.c
@@ -100,4 +100,14 @@ int get_write_protect_state(void)
/* WP is enabled when the pin is reading high. */
return ssus_get_gpio(WP_STATUS_PAD);
-} \ No newline at end of file
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/ninja/dsdt.asl b/src/mainboard/google/ninja/dsdt.asl
index 6475e1c5cf..a37756ff59 100644
--- a/src/mainboard/google/ninja/dsdt.asl
+++ b/src/mainboard/google/ninja/dsdt.asl
@@ -44,7 +44,6 @@ DefinitionBlock(
#include "acpi/dptf.asl"
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/ninja/mainboard.c b/src/mainboard/google/ninja/mainboard.c
index a5d171eac7..df9ecfae39 100644
--- a/src/mainboard/google/ninja/mainboard.c
+++ b/src/mainboard/google/ninja/mainboard.c
@@ -34,6 +34,7 @@
#include "onboard.h"
#include <soc/gpio.h>
#include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -144,6 +145,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
diff --git a/src/mainboard/google/panther/acpi/chromeos.asl b/src/mainboard/google/panther/acpi/chromeos.asl
deleted file mode 100644
index d77a79ef2f..0000000000
--- a/src/mainboard/google/panther/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 12, "LynxPoint" }, // recovery button
- Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c
index 014bb7e7e4..4ee6810c8d 100644
--- a/src/mainboard/google/panther/chromeos.c
+++ b/src/mainboard/google/panther/chromeos.c
@@ -92,3 +92,13 @@ void init_bootmode_straps(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
}
#endif
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl
index 6fdb48b383..66cc041caa 100644
--- a/src/mainboard/google/panther/dsdt.asl
+++ b/src/mainboard/google/panther/dsdt.asl
@@ -54,7 +54,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c
index 68932cf649..661e507182 100644
--- a/src/mainboard/google/panther/mainboard.c
+++ b/src/mainboard/google/panther/mainboard.c
@@ -29,6 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <drivers/intel/gma/int15.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@@ -51,6 +52,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/parrot/acpi/chromeos.asl b/src/mainboard/google/parrot/acpi/chromeos.asl
deleted file mode 100644
index b7541832aa..0000000000
--- a/src/mainboard/google/parrot/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
- Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
- Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index c898f0e39c..4dcbfa5f40 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -23,6 +23,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/compal/ene932/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
@@ -122,3 +123,14 @@ int parrot_ec_running_ro(void)
{
return !get_gpio(68);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 4b0e7305a0..3e13a41c12 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c
index a2b71692aa..4d357f898b 100644
--- a/src/mainboard/google/parrot/mainboard.c
+++ b/src/mainboard/google/parrot/mainboard.c
@@ -32,6 +32,7 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/compal/ene932/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -81,6 +82,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = parrot_onboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/peppy/acpi/chromeos.asl b/src/mainboard/google/peppy/acpi/chromeos.asl
deleted file mode 100644
index 673985fc25..0000000000
--- a/src/mainboard/google/peppy/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
- Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c
index 1659d9cc87..a8cef3279b 100644
--- a/src/mainboard/google/peppy/chromeos.c
+++ b/src/mainboard/google/peppy/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
@@ -86,3 +87,13 @@ int get_write_protect_state(void)
{
return get_gpio(58);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl
index 9e5a114938..83305abd3c 100644
--- a/src/mainboard/google/peppy/dsdt.asl
+++ b/src/mainboard/google/peppy/dsdt.asl
@@ -52,7 +52,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c
index b9ce50eba9..10252d82b1 100644
--- a/src/mainboard/google/peppy/mainboard.c
+++ b/src/mainboard/google/peppy/mainboard.c
@@ -29,6 +29,7 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
@@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl
deleted file mode 100644
index 3072ecaaa6..0000000000
--- a/src/mainboard/google/rambi/acpi/chromeos.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: On Bay Trail we need to encode gpios within the 3 separate banks
- * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
- * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
- */
-
-Name(OIPG, Package() {
- // No physical recovery button
- Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" },
- Package () { 0x0003, 1, 0x2006, "BayTrail" },
-})
diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c
index 1006484e66..4304179d4b 100644
--- a/src/mainboard/google/rambi/chromeos.c
+++ b/src/mainboard/google/rambi/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <soc/gpio.h>
#include <vboot/vboot_common.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
@@ -111,3 +112,13 @@ int get_write_protect_state(void)
/* WP is enabled when the pin is reading high. */
return ssus_get_gpio(WP_STATUS_PAD);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl
index 6475e1c5cf..a37756ff59 100644
--- a/src/mainboard/google/rambi/dsdt.asl
+++ b/src/mainboard/google/rambi/dsdt.asl
@@ -44,7 +44,6 @@ DefinitionBlock(
#include "acpi/dptf.asl"
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index 29cebb120d..adbfd96b3d 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -34,6 +34,7 @@
#include "onboard.h"
#include <soc/gpio.h>
#include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -163,6 +164,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
diff --git a/src/mainboard/google/reef/acpi/chromeos.asl b/src/mainboard/google/reef/acpi/chromeos.asl
deleted file mode 100644
index bec6bcb80a..0000000000
--- a/src/mainboard/google/reef/acpi/chromeos.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio_defs.h>
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
-})
diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c
index 4de6a70ce9..5c526dc6e4 100644
--- a/src/mainboard/google/reef/chromeos.c
+++ b/src/mainboard/google/reef/chromeos.c
@@ -19,6 +19,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/gpio.h>
#include "ec.h"
+#include "gpio.h"
#define GPIO_PCH_WP GPIO_75
#define GPIO_EC_IN_RW GPIO_41
@@ -69,3 +70,13 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+ CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 7a88fb648f..6243c72b15 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -38,7 +38,6 @@ DefinitionBlock(
}
/* Chrome OS specific */
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c
index def6900cf0..0c4ba8dc23 100644
--- a/src/mainboard/google/reef/mainboard.c
+++ b/src/mainboard/google/reef/mainboard.c
@@ -20,6 +20,7 @@
#include <nhlt.h>
#include <soc/gpio.h>
#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "gpio.h"
@@ -83,6 +84,7 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(device_t dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/rikku/acpi/chromeos.asl b/src/mainboard/google/rikku/acpi/chromeos.asl
deleted file mode 100644
index bad5f472b6..0000000000
--- a/src/mainboard/google/rikku/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
- Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c
index d440968c41..b007484089 100644
--- a/src/mainboard/google/rikku/chromeos.c
+++ b/src/mainboard/google/rikku/chromeos.c
@@ -93,3 +93,13 @@ void save_chromeos_gpios(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
}
#endif
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/rikku/dsdt.asl b/src/mainboard/google/rikku/dsdt.asl
index 663b3c5fb1..edb04f05b6 100644
--- a/src/mainboard/google/rikku/dsdt.asl
+++ b/src/mainboard/google/rikku/dsdt.asl
@@ -46,7 +46,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/rikku/mainboard.c b/src/mainboard/google/rikku/mainboard.c
index 16fe630c14..e3eaf4ec5f 100644
--- a/src/mainboard/google/rikku/mainboard.c
+++ b/src/mainboard/google/rikku/mainboard.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
void mainboard_suspend_resume(void)
@@ -35,6 +36,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/samus/acpi/chromeos.asl b/src/mainboard/google/samus/acpi/chromeos.asl
deleted file mode 100644
index 604cd7d0a1..0000000000
--- a/src/mainboard/google/samus/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name (OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button
- Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect
-})
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
index 51f2f2ebf6..7010ac9b6d 100644
--- a/src/mainboard/google/samus/chromeos.c
+++ b/src/mainboard/google/samus/chromeos.c
@@ -93,3 +93,13 @@ int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_ACPI_DEVICE_NAME),
+ CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_ACPI_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl
index 34071b186f..02e63637a7 100644
--- a/src/mainboard/google/samus/dsdt.asl
+++ b/src/mainboard/google/samus/dsdt.asl
@@ -47,7 +47,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c
index 54c6283fe1..9fa9c57783 100644
--- a/src/mainboard/google/samus/mainboard.c
+++ b/src/mainboard/google/samus/mainboard.c
@@ -28,6 +28,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "board_version.h"
#include "ec.h"
@@ -51,6 +52,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/stout/acpi/chromeos.asl b/src/mainboard/google/stout/acpi/chromeos.asl
deleted file mode 100644
index ddabdc8237..0000000000
--- a/src/mainboard/google/stout/acpi/chromeos.asl
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- // No GPIO for recovery mode, developer mode, or firmware write protect
- // on stout - note: all virtual pins are active HIGH polarity on stout.
- Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
- Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
- Package() { 0x003, 0, 7, "PantherPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 4c7a9f5037..cbb9574a91 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -22,6 +22,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include <ec/quanta/it8518/ec.h>
@@ -133,3 +134,14 @@ int get_recovery_mode_switch(void)
return ec_in_rec_mode;
#endif
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
index 723cc718a3..3a822edeb5 100644
--- a/src/mainboard/google/stout/dsdt.asl
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
index 258131024c..4e3839f02b 100644
--- a/src/mainboard/google/stout/mainboard.c
+++ b/src/mainboard/google/stout/mainboard.c
@@ -32,6 +32,7 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/quanta/it8518/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -66,6 +67,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/google/tidus/acpi/chromeos.asl b/src/mainboard/google/tidus/acpi/chromeos.asl
deleted file mode 100644
index 492ee6b272..0000000000
--- a/src/mainboard/google/tidus/acpi/chromeos.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
- Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/google/tidus/chromeos.c b/src/mainboard/google/tidus/chromeos.c
index 13fbfc3dea..710ab48d9e 100644
--- a/src/mainboard/google/tidus/chromeos.c
+++ b/src/mainboard/google/tidus/chromeos.c
@@ -93,3 +93,13 @@ void save_chromeos_gpios(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
}
#endif
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/tidus/dsdt.asl b/src/mainboard/google/tidus/dsdt.asl
index e0786940c9..c3d1fc9171 100644
--- a/src/mainboard/google/tidus/dsdt.asl
+++ b/src/mainboard/google/tidus/dsdt.asl
@@ -46,7 +46,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/google/tidus/mainboard.c b/src/mainboard/google/tidus/mainboard.c
index 3287a7e6a2..1d65829add 100644
--- a/src/mainboard/google/tidus/mainboard.c
+++ b/src/mainboard/google/tidus/mainboard.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
void mainboard_suspend_resume(void)
@@ -35,6 +36,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/amenia/acpi/chromeos.asl b/src/mainboard/intel/amenia/acpi/chromeos.asl
deleted file mode 100644
index 31d0afc8c3..0000000000
--- a/src/mainboard/intel/amenia/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio_defs.h>
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
-})
diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c
index b6669bf0e0..4cfc2a62a9 100644
--- a/src/mainboard/intel/amenia/chromeos.c
+++ b/src/mainboard/intel/amenia/chromeos.c
@@ -18,6 +18,7 @@
#include "ec.h"
#include <ec/google/chromeec/ec.h>
+#include <soc/gpio_defs.h>
#include <vendorcode/google/chromeos/chromeos.h>
int get_lid_switch(void)
@@ -48,3 +49,13 @@ int get_write_protect_state(void)
{
return 0;
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+ CROS_GPIO_WP_AH(PAD_NW(GPIO_75), GPIO_COMM_NW_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 7602b1e80d..9314469d88 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -39,10 +39,7 @@ DefinitionBlock(
}
}
- #if IS_ENABLED(CONFIG_CHROMEOS)
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
- #endif
/* Mainboard Specific devices */
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl
deleted file mode 100644
index 9c49265331..0000000000
--- a/src/mainboard/intel/baskingridge/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery
- Package () { 0x0002, 0, 48, "LynxPoint" }, // developer
- Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 94e8d89a06..1666fc5528 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -102,3 +103,14 @@ int get_write_protect_state(void)
{
return 0;
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl
index 5cd0ffb91b..e4b489cda5 100644
--- a/src/mainboard/intel/baskingridge/dsdt.asl
+++ b/src/mainboard/intel/baskingridge/dsdt.asl
@@ -48,7 +48,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c
index 4c7baca5eb..dbf3574e34 100644
--- a/src/mainboard/intel/baskingridge/mainboard.c
+++ b/src/mainboard/intel/baskingridge/mainboard.c
@@ -28,6 +28,7 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -35,13 +36,12 @@ void mainboard_suspend_resume(void)
outb(0xcb, 0xb2);
}
-
-
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
deleted file mode 100644
index 9f2e54a9d0..0000000000
--- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
- Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
- Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index bb4ebe9f54..896f8767f8 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -91,3 +92,14 @@ int get_recovery_mode_switch(void)
/* Recovery: GPIO22, active low */
return !get_gpio(22);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl
index 8d9e281def..a31c415000 100644
--- a/src/mainboard/intel/emeraldlake2/dsdt.asl
+++ b/src/mainboard/intel/emeraldlake2/dsdt.asl
@@ -49,7 +49,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
index a0fd9e831f..654b1de476 100644
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ b/src/mainboard/intel/emeraldlake2/mainboard.c
@@ -28,12 +28,14 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl
deleted file mode 100644
index 4fc5f22984..0000000000
--- a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
- /* No physical recovery GPIO. */
- Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
- /* Firmware write protect GPIO. */
- Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})
diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c
index 1e0bd3c093..daa85c69e0 100644
--- a/src/mainboard/intel/kunimitsu/chromeos.c
+++ b/src/mainboard/intel/kunimitsu/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl
index c9e13e7e45..b5a37c68cc 100644
--- a/src/mainboard/intel/kunimitsu/dsdt.asl
+++ b/src/mainboard/intel/kunimitsu/dsdt.asl
@@ -45,7 +45,6 @@ DefinitionBlock(
}
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c
index d634fac147..9f79db6ebc 100644
--- a/src/mainboard/intel/kunimitsu/mainboard.c
+++ b/src/mainboard/intel/kunimitsu/mainboard.c
@@ -22,6 +22,7 @@
#include <stdlib.h>
#include <string.h>
#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "gpio.h"
@@ -99,6 +100,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl
deleted file mode 100644
index c470ca3e9d..0000000000
--- a/src/mainboard/intel/strago/acpi/chromeos.asl
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: We need to encode gpios within the 4 separate banks
- * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
- * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
- */
-
-Name(OIPG, Package() {
- /* No physical recovery button */
- Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
- Package () { 0x0003, 1, 0x10013, "Braswell" },
-})
diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c
index 0e072f0dc0..0fb98111a8 100644
--- a/src/mainboard/intel/strago/chromeos.c
+++ b/src/mainboard/intel/strago/chromeos.c
@@ -118,3 +118,13 @@ int get_write_protect_state(void)
/* WP is enabled when the pin is reading high. */
return !!gpio_get(WP_GPIO);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl
index f1248d8d7c..59af6ddb95 100644
--- a/src/mainboard/intel/strago/dsdt.asl
+++ b/src/mainboard/intel/strago/dsdt.asl
@@ -54,7 +54,6 @@ DefinitionBlock(
#include <soc/intel/common/acpi/wifi.asl>
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c
index 0566c8e2f6..71ba62b13e 100644
--- a/src/mainboard/intel/strago/mainboard.c
+++ b/src/mainboard/intel/strago/mainboard.c
@@ -18,6 +18,7 @@
#include <bootstate.h>
#include <device/device.h>
#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(device_t dev)
@@ -32,6 +33,7 @@ static void mainboard_init(device_t dev)
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl
deleted file mode 100644
index 4257e7ddfe..0000000000
--- a/src/mainboard/intel/wtm2/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery
- Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer
- Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index feee0cbc32..862f4a411c 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
/* Compile-time settings for developer and recovery mode. */
#define DEV_MODE_SETTING 1
@@ -55,3 +56,14 @@ int get_write_protect_state(void)
{
return 0;
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index 1601483921..410f6d20aa 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -49,7 +49,6 @@ DefinitionBlock(
#include "acpi/thermal.asl"
// Chrome OS specific
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c
index 253e8ff03c..ffb5b86a18 100644
--- a/src/mainboard/intel/wtm2/mainboard.c
+++ b/src/mainboard/intel/wtm2/mainboard.c
@@ -27,6 +27,7 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -39,6 +40,7 @@ void mainboard_suspend_resume(void)
static void mainboard_enable(device_t dev)
{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
deleted file mode 100644
index f3bb40bbc9..0000000000
--- a/src/mainboard/samsung/lumpy/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
- Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
- Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 9ee32bb7c6..71d82b5e37 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -21,6 +21,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 24
#define GPIO_REC_MODE 42
@@ -135,3 +136,14 @@ void init_bootmode_straps(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index ed3a84a390..28b0c1b77d 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -52,7 +52,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
index 95a75312e3..3de067eb82 100644
--- a/src/mainboard/samsung/lumpy/mainboard.c
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -31,6 +31,7 @@
#include "onboard.h"
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -98,6 +99,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = lumpy_onboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl
deleted file mode 100644
index 5d69251f83..0000000000
--- a/src/mainboard/samsung/stumpy/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
- Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
- Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
- Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 5f2a062065..96d2b125d7 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 68
#define GPIO_REC_MODE 42
@@ -132,3 +133,14 @@ void init_bootmode_straps(void)
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
#endif
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 4b0e7305a0..3e13a41c12 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -50,7 +50,6 @@ DefinitionBlock(
}
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
index a0fd9e831f..654b1de476 100644
--- a/src/mainboard/samsung/stumpy/mainboard.c
+++ b/src/mainboard/samsung/stumpy/mainboard.c
@@ -28,12 +28,14 @@
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}