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authorJulius Werner <jwerner@chromium.org>2014-10-06 13:41:28 -0700
committerAaron Durbin <adurbin@google.com>2015-04-04 15:02:24 +0200
commitb6092b7e396d5e7ab55cb7c11375b6a8fec7cd61 (patch)
tree56d05fa074c4df23708fe05a6f1dc87b69c67daf /src/mainboard
parent46826c36bf1af1dcb4535f0838933f01f600a9d7 (diff)
downloadcoreboot-b6092b7e396d5e7ab55cb7c11375b6a8fec7cd61.tar.xz
veyron_pinky/rk3288: Use KHz, MHz and GHz constants
Use the previously added frequency constants in patch titled 'stddef: Add KHz, MHz and GHz constants'. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac Reviewed-on: http://review.coreboot.org/9254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/veyron_pinky/bootblock.c4
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc2
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc2
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc2
4 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index d4f82decff..3ed8e273c7 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -32,11 +32,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
index 409a7cad35..07161c0dfa 100644
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
@@ -69,7 +69,7 @@
.noc_timing = 0x2891E41D,
.noc_activate = 0x5B6,
.ddrconfig = 3,
- .ddr_freq = 533000000,
+ .ddr_freq = 533*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
index 3fdbecf6a8..f5793d1561 100644
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
@@ -70,7 +70,7 @@
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
- .ddr_freq = 666000000,
+ .ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
index 315e542c39..f42f1b1b8b 100644
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
@@ -70,7 +70,7 @@
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
- .ddr_freq = 533000000,
+ .ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,