diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-24 08:53:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-26 13:38:46 +0200 |
| commit | b87a734771449ed06cd91621da4c893a1ad722b0 (patch) | |
| tree | 9ca49309fba09071aeaab4cecc9e80ed94ca9a0e /src/mainboard | |
| parent | 8da96e57c89860f429f1bf590c10fa364b8019d4 (diff) | |
| download | coreboot-b87a734771449ed06cd91621da4c893a1ad722b0.tar.xz | |
mainboard/*/*/dsdt.asl: Use tabs for indents
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
23 files changed, 2402 insertions, 2402 deletions
diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 9dfdbb17b9..37b9ae17a5 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -1534,8 +1534,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1578,20 +1578,20 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index ff92d36c3a..6411968949 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -1540,8 +1540,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1584,20 +1584,20 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 2c2ae76d93..b6a9c3c52e 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -15,1155 +15,1155 @@ /* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00010001 /* OEM Revision */ - ) + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ - - /* Some global data */ - Name(OSV, Ones) /* Assume nothing */ - Name(GPIC, 0x1) /* Assume PIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C002, /* name space name */ - 2, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C003, /* name space name */ - 3, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSV, Ones) /* Assume nothing */ + Name(GPIC, 0x1) /* Assume PIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C001, /* name space name */ + 1, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } Processor( - C004, /* name space name */ - 4, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { } Processor( - C005, /* name space name */ - 5, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { } Processor( - C006, /* name space name */ - 6, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { } Processor( - C007, /* name space name */ - 7, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) + Field(PIRQ, ByteAcc, NoLock, Preserve) { + PIDX, 0x00000008, + PDAT, 0x00000008, /* Offset: 1h */ + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + Offset(0x10), + PIRS, 0x00000008, + Offset(0x13), + HDAD, 0x00000008, + , 0x00000008, + GEC, 0x00000008, + Offset(0x30), + USB1, 0x00000008, + USB2, 0x00000008, + USB3, 0x00000008, + USB4, 0x00000008, + USB5, 0x00000008, + USB6, 0x00000008, + USB7, 0x00000008, + Offset(0x40), + IDE, 0x00000008, + SATA, 0x00000008, + Offset(0x50), + GPP0, 0x00000008, + GPP1, 0x00000008, + GPP2, 0x00000008, + GPP3, 0x00000008 + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ + OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) + Field(PMRG, ByteAcc, NoLock, Preserve) { + PMRI, 0x00000008, + PMRD, 0x00000008, + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { + Offset(0x24), + MMSO,32, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x50), + HPAD,32, + Offset(0x60), + P1EB,16, + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xC8), + ,2, + SPRE,1, + TPDE,1, + Offset(0xF0), + ,3, + RSTU,1 + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, NoLock, Preserve) { + ,14, + PEWS,1, + WSTA,1, + ,14, + PEWD,1 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } +} + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + /* Debug Port registers, 80h. */ + OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) + Field(DBBG, ByteAcc, NoLock, Preserve) { + DBG8, 0x00000008, + } + + Method(_PIC, 1) { + Store(Arg0, GPIC) + If (GPIC) { + Store(0xAA, \_SB.DBG8) + \_SB.DSPI() + } else { + Store(0xAC, \_SB.DBG8) + } + } + + Method(DSPI, 0) { + \_SB.GRUA(0x1F) + \_SB.GRUB(0x1F) + \_SB.GRUC(0x1F) + \_SB.GRUD(0x1F) + Store(0x1F, PIRE) + Store(0x1F, PIRF) + Store(0x1F, PIRG) + Store(0x1F, PIRH) + } + + Method(GRUA, 1) { + Store(Arg0, PIRA) + Store(Arg0, HDAD) + Store(Arg0, GEC) + Store(Arg0, GPP0) + Store(Arg0, GPP0) + } + + Method(GRUB, 1) { + Store(Arg0, PIRB) + Store(Arg0, USB2) + Store(Arg0, USB4) + Store(Arg0, USB6) + Store(Arg0, GPP1) + Store(Arg0, IDE) + } + + Method(GRUC, 1) { + Store(Arg0, PIRC) + Store(Arg0, USB1) + Store(Arg0, USB3) + Store(Arg0, USB5) + Store(Arg0, USB7) + Store(Arg0, GPP2) + } + + Method(GRUD, 1) { + Store(Arg0, PIRD) + Store(Arg0, SATA) + Store(Arg0, GPP3) + } + + Name(IRQB, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 15 + }}) + + Name(IRQP, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 3, 4, 5, 7, 10, 11, 12, 14, 15 + } + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUA(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUA(Local0) + } + } + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUB(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUB(Local0) + } + } + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUC(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUC(Local0) + } + } + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUD(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUD(Local0) + } + } + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRE) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRE) + } + } + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRF) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRF) + } + } + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRG) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRG) + } + } + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRH) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRH) + } + } + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PEWS, Local0) + Store(Local0, PEWS) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + } /* End Scope GPE */ + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + External (TOM3) + External (TOM4) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + Method(_PRT,0) { + If(GPIC){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Method(_STA,0) { + Return(0x0F) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Method(_PRT,0) { + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* The external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Method(_PRT,0) { + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Method(_PRT,0) { + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Method(_PRT,0) { + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Method(_PRT,0) { + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Method(_PRT,0) { + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + Device(PE20) { + Name(_ADR, 0x00150000) + Method(_PRT,0) { + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Method(_PRT,0) { + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Method(_PRT,0) { + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Method(_PRT,0) { + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* Describe the Southbridge devices */ + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + } + } /* end AZHD */ + + Device(GEC) { + Name(_ADR, 0x00140006) + } /* end GEC */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + } /* end UOH1 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + } /* end UOH3 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + } /* end UEH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + } /* end UOH2 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + } /* end UOH4 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + } /* end UOH5 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + } /* end XHC0 */ + + Device(XHC1) { + Name(_ADR, 0x00100001) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {8} + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {0} + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IRQNoFlags () {12} + }) + Method (_STA, 0) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + } /* end LIBR */ + + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method(_STA, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(0x0F) + } + Return(0x0) + } + Method(_CRS, 0) { + CreateDWordField(CRS, 0x0A, HPEB) + Store(HPAD, Local0) + And(Local0, 0xFFFFFFC0, HPEB) + Return(CRS) + } + } /* End Device(_SB.PCI0.HPET) */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + Store(\_SB.PCI0.TOM1, MM1B) + Subtract(PCBA, MM1B, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) /* sata is invisible */ } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) - Field(PIRQ, ByteAcc, NoLock, Preserve) { - PIDX, 0x00000008, - PDAT, 0x00000008, /* Offset: 1h */ - } - IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - Offset(0x10), - PIRS, 0x00000008, - Offset(0x13), - HDAD, 0x00000008, - , 0x00000008, - GEC, 0x00000008, - Offset(0x30), - USB1, 0x00000008, - USB2, 0x00000008, - USB3, 0x00000008, - USB4, 0x00000008, - USB5, 0x00000008, - USB6, 0x00000008, - USB7, 0x00000008, - Offset(0x40), - IDE, 0x00000008, - SATA, 0x00000008, - Offset(0x50), - GPP0, 0x00000008, - GPP1, 0x00000008, - GPP2, 0x00000008, - GPP3, 0x00000008 - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ - OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) - Field(PMRG, ByteAcc, NoLock, Preserve) { - PMRI, 0x00000008, - PMRD, 0x00000008, - } - IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { - Offset(0x24), - MMSO,32, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x50), - HPAD,32, - Offset(0x60), - P1EB,16, - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xC8), - ,2, - SPRE,1, - TPDE,1, - Offset(0xF0), - ,3, - RSTU,1 - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1E0, SystemIO, P1EB, 0x04) - Field(P1E0, ByteAcc, NoLock, Preserve) { - ,14, - PEWS,1, - WSTA,1, - ,14, - PEWD,1 - } - - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - /* Debug Port registers, 80h. */ - OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) - Field(DBBG, ByteAcc, NoLock, Preserve) { - DBG8, 0x00000008, - } - - Method(_PIC, 1) { - Store(Arg0, GPIC) - If (GPIC) { - Store(0xAA, \_SB.DBG8) - \_SB.DSPI() - } else { - Store(0xAC, \_SB.DBG8) - } - } - - Method(DSPI, 0) { - \_SB.GRUA(0x1F) - \_SB.GRUB(0x1F) - \_SB.GRUC(0x1F) - \_SB.GRUD(0x1F) - Store(0x1F, PIRE) - Store(0x1F, PIRF) - Store(0x1F, PIRG) - Store(0x1F, PIRH) - } - - Method(GRUA, 1) { - Store(Arg0, PIRA) - Store(Arg0, HDAD) - Store(Arg0, GEC) - Store(Arg0, GPP0) - Store(Arg0, GPP0) - } - - Method(GRUB, 1) { - Store(Arg0, PIRB) - Store(Arg0, USB2) - Store(Arg0, USB4) - Store(Arg0, USB6) - Store(Arg0, GPP1) - Store(Arg0, IDE) - } - - Method(GRUC, 1) { - Store(Arg0, PIRC) - Store(Arg0, USB1) - Store(Arg0, USB3) - Store(Arg0, USB5) - Store(Arg0, USB7) - Store(Arg0, GPP2) - } - - Method(GRUD, 1) { - Store(Arg0, PIRD) - Store(Arg0, SATA) - Store(Arg0, GPP3) - } - - Name(IRQB, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) { - 15 - }}) - - Name(IRQP, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) { - 3, 4, 5, 7, 10, 11, 12, 14, 15 - }}) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUA(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUA(Local0) - } - } - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUB(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUB(Local0) - } - } - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUC(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUC(Local0) - } - } - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - \_SB.GRUD(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - \_SB.GRUD(Local0) - } - } - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRE) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRE) - } - } - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRF) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRF) - } - } - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRG) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRG) - } - } - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRH) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRH) - } - } - } /* End Scope(_SB) */ - - - /* Supported sleep states: */ - Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - - If (LAnd(SSFG, 0x01)) { - Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ - } - If (LAnd(SSFG, 0x02)) { - Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ - } - If (LAnd(SSFG, 0x04)) { - Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ - } - If (LAnd(SSFG, 0x08)) { - Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ - } - - Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ - - Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ - Name(CSMS, 0) /* Current System State */ - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PEWS, Local0) - Store(Local0, PEWS) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - } /* End Scope GPE */ - - /* South Bridge */ - Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - External (TOM3) - External (TOM4) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - Method(_PRT,0) { - If(GPIC){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Method(_STA,0) { - Return(0x0F) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Method(_PRT,0) { - If(GPIC){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* The external GFX bridge */ - Device(PBR3) { - Name(_ADR, 0x00030000) - Method(_PRT,0) { - If(GPIC){ Return(APS3) } /* APIC mode */ - Return (PS3) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR3 */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Method(_PRT,0) { - If(GPIC){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Method(_PRT,0) { - If(GPIC){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Method(_PRT,0) { - If(GPIC){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Method(_PRT,0) { - If(GPIC){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Method(_PRT,0) { - If(GPIC){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Method(_PRT,0) { - If(GPIC){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Method(_PRT,0) { - If(GPIC){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Method(_PRT,0) { - If(GPIC){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* Describe the Southbridge devices */ - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - } - } /* end AZHD */ - - Device(GEC) { - Name(_ADR, 0x00140006) - } /* end GEC */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - } /* end UOH1 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - } /* end UOH3 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - } /* end UEH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - } /* end UOH2 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - } /* end UOH4 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - } /* end UOH5 */ - - Device(XHC0) { - Name(_ADR, 0x00100000) - } /* end XHC0 */ - - Device(XHC1) { - Name(_ADR, 0x00100001) - } /* end XHC1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() {8} - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Method(_CRS, 0) { - If(LAnd(HPAD, 0xFFFFFF00)) { - Return(BUF0) - } - Return(BUF1) - } - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() {0} - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Method(_CRS, 0) { - If(LAnd(HPAD, 0xFFFFFF00)) { - Return(BUF0) - } - Return(BUF1) - } - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device (PS2M) { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () { - IRQNoFlags () {12} - }) - Method (_STA, 0) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { - Return (0x0F) - } Else { - Return (0x00) - } - } - } - - Device (PS2K) { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } - } /* end LIBR */ - - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(HPET) { - Name(_HID,EISAID("PNP0103")) - Name(CRS, ResourceTemplate() { - IRQNoFlags() {0} - IRQNoFlags() {8} - Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) - }) - Method(_STA, 0) { - If(LAnd(HPAD, 0xFFFFFF00)) { - Return(0x0F) - } - Return(0x0) - } - Method(_CRS, 0) { - CreateDWordField(CRS, 0x0A, HPEB) - Store(HPAD, Local0) - And(Local0, 0xFFFFFFC0, HPEB) - Return(CRS) - } - } /* End Device(_SB.PCI0.HPET) */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - Store(\_SB.PCI0.TOM1, MM1B) - Subtract(PCBA, MM1B, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ + } /* End \_SB scope */ } /* End of ASL file */ diff --git a/src/mainboard/amd/serengeti_cheetah/dsdt.asl b/src/mainboard/amd/serengeti_cheetah/dsdt.asl index 6a77f125dd..e9f1f471b9 100644 --- a/src/mainboard/amd/serengeti_cheetah/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah/dsdt.asl @@ -15,209 +15,209 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) { - Scope (_PR) - { - Processor (CPU0, 0x00, 0x0000C010, 0x06) {} - Processor (CPU1, 0x01, 0x00000000, 0x00) {} - Processor (CPU2, 0x02, 0x00000000, 0x00) {} - Processor (CPU3, 0x03, 0x00000000, 0x00) {} - - } - - Method (FWSO, 0, NotSerialized) { } - - Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) - Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 }) - Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 }) - Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 }) - - Scope (_SB) - { - Device (PCI0) - { - /* BUS0 root bus */ - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - External (CBST) - - - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - \_SB.OSVR () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci0_hc.asl" - - } - Device (PCI1) - { - Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.CBST) - } + Scope (_PR) + { + Processor (CPU0, 0x00, 0x0000C010, 0x06) {} + Processor (CPU1, 0x01, 0x00000000, 0x00) {} + Processor (CPU2, 0x02, 0x00000000, 0x00) {} + Processor (CPU3, 0x03, 0x00000000, 0x00) {} + + } + + Method (FWSO, 0, NotSerialized) { } + + Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) + Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 }) + Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 }) + Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 }) + + Scope (_SB) + { + Device (PCI0) + { + /* BUS0 root bus */ + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + External (CBST) + + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x000CFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00010000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + \_SB.OSVR () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci0_hc.asl" + + } + Device (PCI1) + { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00000000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + Return (\_SB.PCI0.CBST) + } Name (_BBN, 0x00) - } - - - } - - Scope (_GPE) - { - Method (_L08, 0, NotSerialized) - { - Notify (\_SB.PCI0, 0x02) //PME# Wakeup - } - - Method (_L0F, 0, NotSerialized) - { - Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - } - - Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B - { - Notify (\_SB.PCI0.PG0B, 0x02) - } - - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A - { - Notify (\_SB.PCI0.PG0A, 0x02) - } - } - - Method (_PTS, 1, NotSerialized) - { - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG1) - } + } + + + } + + Scope (_GPE) + { + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0, 0x02) //PME# Wakeup + } + + Method (_L0F, 0, NotSerialized) + { + Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + } + + Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B + { + Notify (\_SB.PCI0.PG0B, 0x02) + } + + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + { + Notify (\_SB.PCI0.PG0A, 0x02) + } + } + + Method (_PTS, 1, NotSerialized) + { + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) + } /* - Method (_WAK, 1, NotSerialized) - { - Or (Arg0, 0xE0, Local0) - Store (Local0, DBG1) - } + Method (_WAK, 1, NotSerialized) + { + Or (Arg0, 0xE0, Local0) + Store (Local0, DBG1) + } */ - Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode - Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method - { - Store (Arg0, PICF) - } - - OperationRegion (DEBG, SystemIO, 0x80, 0x01) - Field (DEBG, ByteAcc, Lock, Preserve) - { - DBG1, 8 - } - - OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) - Field (EXTM, WordAcc, Lock, Preserve) - { - AMEM, 32 - } - - OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) - Field (VGAM, ByteAcc, Lock, Preserve) - { - VGA1, 8 - } - - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } - - OperationRegion (GSTS, SystemIO, 0xC028, 0x02) - Field (GSTS, ByteAcc, NoLock, Preserve) - { - , 4, - IRQR, 1 - } - - OperationRegion (Z007, SystemIO, 0x21, 0x01) - Field (Z007, ByteAcc, NoLock, Preserve) - { - Z008, 8 - } - - OperationRegion (Z009, SystemIO, 0xA1, 0x01) - Field (Z009, ByteAcc, NoLock, Preserve) - { - Z00A, 8 - } - - #include "northbridge/amd/amdk8/util.asl" + Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode + Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method + { + Store (Arg0, PICF) + } + + OperationRegion (DEBG, SystemIO, 0x80, 0x01) + Field (DEBG, ByteAcc, Lock, Preserve) + { + DBG1, 8 + } + + OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) + Field (EXTM, WordAcc, Lock, Preserve) + { + AMEM, 32 + } + + OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) + Field (VGAM, ByteAcc, Lock, Preserve) + { + VGA1, 8 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + OperationRegion (GSTS, SystemIO, 0xC028, 0x02) + Field (GSTS, ByteAcc, NoLock, Preserve) + { + , 4, + IRQR, 1 + } + + OperationRegion (Z007, SystemIO, 0x21, 0x01) + Field (Z007, ByteAcc, NoLock, Preserve) + { + Z008, 8 + } + + OperationRegion (Z009, SystemIO, 0xA1, 0x01) + Field (Z009, ByteAcc, NoLock, Preserve) + { + Z00A, 8 + } + + #include "northbridge/amd/amdk8/util.asl" } diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 2014a91f42..f257f23ec1 100644 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -220,12 +220,12 @@ DefinitionBlock ( PEWD,1 } - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } Scope(\_SB) { /* PCIe Configuration Space for 16 busses */ @@ -1113,7 +1113,7 @@ DefinitionBlock ( Method(_CRS, 0) { /* DBGO("\\_SB\\PCI0\\_CRS\n") */ CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* * Declare memory between TOM1 and 4GB as available * for PCI MMIO. diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index d305af5cd4..dab489b393 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -31,13 +31,13 @@ */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00000001 /* OEM Revision */ - ) + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) { #include "northbridge/amd/amdfam10/amdfam10_util.asl" #include "southbridge/amd/sr5650/acpi/sr5650.asl" @@ -628,10 +628,10 @@ DefinitionBlock ( } Return (0x0) } - Method(_CRS, 0) - { - Return(CRS) - } + Method(_CRS, 0) + { + Return(CRS) + } } /* 0:14.4 PCI Bridge */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index bd4a76f3e2..2f1e86a14b 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -31,13 +31,13 @@ */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00000001 /* OEM Revision */ - ) + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) { #include "northbridge/amd/amdfam10/amdfam10_util.asl" diff --git a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl b/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl index 9d5d520b36..ce01a49db8 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl @@ -31,13 +31,13 @@ */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00000001 /* OEM Revision */ - ) + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) { #include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index aa12e0e113..42242bfb67 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -31,13 +31,13 @@ */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00000001 /* OEM Revision */ - ) + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00000001 /* OEM Revision */ + ) { #include "northbridge/amd/amdfam10/amdfam10_util.asl" #include "southbridge/amd/sr5650/acpi/sr5650.asl" @@ -630,10 +630,10 @@ DefinitionBlock ( } Return (0x0) } - Method(_CRS, 0) - { - Return(CRS) - } + Method(_CRS, 0) + { + Return(CRS) + } } /* 0:14.4 PCI Bridge */ diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 6f02e8b96f..e1d517f370 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -1540,8 +1540,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1584,20 +1584,20 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index c6ced3d2a5..81504ef6ac 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -1534,8 +1534,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1578,20 +1578,20 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index b02f542d3a..f48280ebe3 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -14,13 +14,13 @@ */ DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision - "CORE", // OEMID - "COREBOOT", // TABLE ID - 0x1 // OEM Revision - ) + "dsdt.aml", // Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "CORE", // OEMID + "COREBOOT", // TABLE ID + 0x1 // OEM Revision + ) { #include "acpi/dbug.asl" @@ -30,13 +30,13 @@ DefinitionBlock ( * PCI Bus definition ****************************************************************/ - Scope(\_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - } - } + Scope(\_SB) { + Device(PCI0) { + Name(_HID, EisaId("PNP0A03")) + Name(_ADR, 0x00) + Name(_UID, 1) + } + } #include "acpi/pci-crs.asl" #include "acpi/hpet.asl" @@ -46,67 +46,67 @@ DefinitionBlock ( * VGA ****************************************************************/ - Scope(\_SB.PCI0) { - Device(VGA) { - Name(_ADR, 0x00020000) - OperationRegion(PCIC, PCI_Config, Zero, 0x4) - Field(PCIC, DWordAcc, NoLock, Preserve) { - VEND, 32 - } - Method(_S1D, 0, NotSerialized) { - Return (0x00) - } - Method(_S2D, 0, NotSerialized) { - Return (0x00) - } - Method(_S3D, 0, NotSerialized) { - If (LEqual(VEND, 0x1001b36)) { - Return (0x03) // QXL - } Else { - Return (0x00) - } - } - } - } + Scope(\_SB.PCI0) { + Device(VGA) { + Name(_ADR, 0x00020000) + OperationRegion(PCIC, PCI_Config, Zero, 0x4) + Field(PCIC, DWordAcc, NoLock, Preserve) { + VEND, 32 + } + Method(_S1D, 0, NotSerialized) { + Return (0x00) + } + Method(_S2D, 0, NotSerialized) { + Return (0x00) + } + Method(_S3D, 0, NotSerialized) { + If (LEqual(VEND, 0x1001b36)) { + Return (0x03) // QXL + } Else { + Return (0x00) + } + } + } + } /**************************************************************** * PIIX4 PM ****************************************************************/ - Scope(\_SB.PCI0) { - Device(PX13) { - Name(_ADR, 0x00010003) - OperationRegion(P13C, PCI_Config, 0x00, 0xff) - } - } + Scope(\_SB.PCI0) { + Device(PX13) { + Name(_ADR, 0x00010003) + OperationRegion(P13C, PCI_Config, 0x00, 0xff) + } + } /**************************************************************** * PIIX3 ISA bridge ****************************************************************/ - Scope(\_SB.PCI0) { - Device(ISA) { - Name(_ADR, 0x00010000) - - /* PIIX PCI to ISA irq remapping */ - OperationRegion(P40C, PCI_Config, 0x60, 0x04) - - /* enable bits */ - Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) { - Offset(0x5f), - , 7, - LPEN, 1, // LPT - Offset(0x67), - , 3, - CAEN, 1, // COM1 - , 3, - CBEN, 1, // COM2 - } - Name(FDEN, 1) - } - } + Scope(\_SB.PCI0) { + Device(ISA) { + Name(_ADR, 0x00010000) + + /* PIIX PCI to ISA irq remapping */ + OperationRegion(P40C, PCI_Config, 0x60, 0x04) + + /* enable bits */ + Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) { + Offset(0x5f), + , 7, + LPEN, 1, // LPT + Offset(0x67), + , 3, + CAEN, 1, // COM1 + , 3, + CBEN, 1, // COM2 + } + Name(FDEN, 1) + } + } #include "acpi/isa.asl" @@ -115,177 +115,177 @@ DefinitionBlock ( * PCI hotplug ****************************************************************/ - Scope(\_SB.PCI0) { - OperationRegion(PCST, SystemIO, 0xae00, 0x08) - Field(PCST, DWordAcc, NoLock, WriteAsZeros) { - PCIU, 32, - PCID, 32, - } - - OperationRegion(SEJ, SystemIO, 0xae08, 0x04) - Field(SEJ, DWordAcc, NoLock, WriteAsZeros) { - B0EJ, 32, - } - - /* Methods called by bulk generated PCI devices below */ - - /* Methods called by hotplug devices */ - Method(PCEJ, 1, NotSerialized) { - // _EJ0 method - eject callback - Store(ShiftLeft(1, Arg0), B0EJ) - Return (0x0) - } - - /* Hotplug notification method supplied by SSDT */ - External(\_SB.PCI0.PCNT, MethodObj) - - /* PCI hotplug notify method */ - Method(PCNF, 0) { - // Local0 = iterator - Store(Zero, Local0) - While (LLess(Local0, 31)) { - Increment(Local0) - If (And(PCIU, ShiftLeft(1, Local0))) { - PCNT(Local0, 1) - } - If (And(PCID, ShiftLeft(1, Local0))) { - PCNT(Local0, 3) - } - } - } - } + Scope(\_SB.PCI0) { + OperationRegion(PCST, SystemIO, 0xae00, 0x08) + Field(PCST, DWordAcc, NoLock, WriteAsZeros) { + PCIU, 32, + PCID, 32, + } + + OperationRegion(SEJ, SystemIO, 0xae08, 0x04) + Field(SEJ, DWordAcc, NoLock, WriteAsZeros) { + B0EJ, 32, + } + + /* Methods called by bulk generated PCI devices below */ + + /* Methods called by hotplug devices */ + Method(PCEJ, 1, NotSerialized) { + // _EJ0 method - eject callback + Store(ShiftLeft(1, Arg0), B0EJ) + Return (0x0) + } + + /* Hotplug notification method supplied by SSDT */ + External(\_SB.PCI0.PCNT, MethodObj) + + /* PCI hotplug notify method */ + Method(PCNF, 0) { + // Local0 = iterator + Store(Zero, Local0) + While (LLess(Local0, 31)) { + Increment(Local0) + If (And(PCIU, ShiftLeft(1, Local0))) { + PCNT(Local0, 1) + } + If (And(PCID, ShiftLeft(1, Local0))) { + PCNT(Local0, 3) + } + } + } + } /**************************************************************** * PCI IRQs ****************************************************************/ - Scope(\_SB) { - Scope(PCI0) { - Name(_PRT, Package() { - /* PCI IRQ routing table, example from ACPI 2.0a specification, - section 6.2.8.1 */ - /* Note: we provide the same info as the PCI routing - table of the Bochs BIOS */ + Scope(\_SB) { + Scope(PCI0) { + Name(_PRT, Package() { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ #define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \ - Package() { nr##ffff, 0, lnk0, 0 }, \ - Package() { nr##ffff, 1, lnk1, 0 }, \ - Package() { nr##ffff, 2, lnk2, 0 }, \ - Package() { nr##ffff, 3, lnk3, 0 } + Package() { nr##ffff, 0, lnk0, 0 }, \ + Package() { nr##ffff, 1, lnk1, 0 }, \ + Package() { nr##ffff, 2, lnk2, 0 }, \ + Package() { nr##ffff, 3, lnk3, 0 } #define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC) #define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD) #define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA) #define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB) - prt_slot0(0x0000), - /* Device 1 is power mgmt device, and can only use irq 9 */ - prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD), - prt_slot2(0x0002), - prt_slot3(0x0003), - prt_slot0(0x0004), - prt_slot1(0x0005), - prt_slot2(0x0006), - prt_slot3(0x0007), - prt_slot0(0x0008), - prt_slot1(0x0009), - prt_slot2(0x000a), - prt_slot3(0x000b), - prt_slot0(0x000c), - prt_slot1(0x000d), - prt_slot2(0x000e), - prt_slot3(0x000f), - prt_slot0(0x0010), - prt_slot1(0x0011), - prt_slot2(0x0012), - prt_slot3(0x0013), - prt_slot0(0x0014), - prt_slot1(0x0015), - prt_slot2(0x0016), - prt_slot3(0x0017), - prt_slot0(0x0018), - prt_slot1(0x0019), - prt_slot2(0x001a), - prt_slot3(0x001b), - prt_slot0(0x001c), - prt_slot1(0x001d), - prt_slot2(0x001e), - prt_slot3(0x001f), - }) - } - - Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) { - PRQ0, 8, - PRQ1, 8, - PRQ2, 8, - PRQ3, 8 - } - - Method(IQST, 1, NotSerialized) { - // _STA method - get status - If (And(0x80, Arg0)) { - Return (0x09) - } - Return (0x0B) - } - Method(IQCR, 1, Serialized) { - // _CRS method - get current settings - Name(PRR0, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 0 } - }) - CreateDWordField(PRR0, 0x05, PRRI) - If (LLess(Arg0, 0x80)) { - Store(Arg0, PRRI) - } - Return (PRR0) - } + prt_slot0(0x0000), + /* Device 1 is power mgmt device, and can only use irq 9 */ + prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD), + prt_slot2(0x0002), + prt_slot3(0x0003), + prt_slot0(0x0004), + prt_slot1(0x0005), + prt_slot2(0x0006), + prt_slot3(0x0007), + prt_slot0(0x0008), + prt_slot1(0x0009), + prt_slot2(0x000a), + prt_slot3(0x000b), + prt_slot0(0x000c), + prt_slot1(0x000d), + prt_slot2(0x000e), + prt_slot3(0x000f), + prt_slot0(0x0010), + prt_slot1(0x0011), + prt_slot2(0x0012), + prt_slot3(0x0013), + prt_slot0(0x0014), + prt_slot1(0x0015), + prt_slot2(0x0016), + prt_slot3(0x0017), + prt_slot0(0x0018), + prt_slot1(0x0019), + prt_slot2(0x001a), + prt_slot3(0x001b), + prt_slot0(0x001c), + prt_slot1(0x001d), + prt_slot2(0x001e), + prt_slot3(0x001f), + }) + } + + Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method(IQST, 1, NotSerialized) { + // _STA method - get status + If (And(0x80, Arg0)) { + Return (0x09) + } + Return (0x0B) + } + Method(IQCR, 1, Serialized) { + // _CRS method - get current settings + Name(PRR0, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 0 } + }) + CreateDWordField(PRR0, 0x05, PRRI) + If (LLess(Arg0, 0x80)) { + Store(Arg0, PRRI) + } + Return (PRR0) + } #define define_link(link, uid, reg) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - 5, 10, 11 \ - } \ - }) \ - Method(_STA, 0, NotSerialized) { \ - Return (IQST(reg)) \ - } \ - Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ - } \ - Method(_CRS, 0, NotSerialized) { \ - Return (IQCR(reg)) \ - } \ - Method(_SRS, 1, NotSerialized) { \ - CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ - } \ - } - - define_link(LNKA, 0, PRQ0) - define_link(LNKB, 1, PRQ1) - define_link(LNKC, 2, PRQ2) - define_link(LNKD, 3, PRQ3) - - Device(LNKS) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Name(_PRS, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 9 } - }) - - // The SCI cannot be disabled and is always attached to GSI 9, - // so these are no-ops. We only need this link to override the - // polarity to active high and match the content of the MADT. - Method(_STA, 0, NotSerialized) { Return (0x0b) } - Method(_DIS, 0, NotSerialized) { } - Method(_CRS, 0, NotSerialized) { Return (_PRS) } - Method(_SRS, 1, NotSerialized) { } - } - } + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + 5, 10, 11 \ + } \ + }) \ + Method(_STA, 0, NotSerialized) { \ + Return (IQST(reg)) \ + } \ + Method(_DIS, 0, NotSerialized) { \ + Or(reg, 0x80, reg) \ + } \ + Method(_CRS, 0, NotSerialized) { \ + Return (IQCR(reg)) \ + } \ + Method(_SRS, 1, NotSerialized) { \ + CreateDWordField(Arg0, 0x05, PRRI) \ + Store(PRRI, reg) \ + } \ + } + + define_link(LNKA, 0, PRQ0) + define_link(LNKB, 1, PRQ1) + define_link(LNKC, 2, PRQ2) + define_link(LNKD, 3, PRQ3) + + Device(LNKS) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Name(_PRS, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 9 } + }) + + // The SCI cannot be disabled and is always attached to GSI 9, + // so these are no-ops. We only need this link to override the + // polarity to active high and match the content of the MADT. + Method(_STA, 0, NotSerialized) { Return (0x0b) } + Method(_DIS, 0, NotSerialized) { } + Method(_CRS, 0, NotSerialized) { Return (_PRS) } + Method(_SRS, 1, NotSerialized) { } + } + } #if 0 #include "acpi/cpu-hotplug.asl" @@ -296,48 +296,48 @@ DefinitionBlock ( * General purpose events ****************************************************************/ - Scope(\_GPE) { - Name(_HID, "ACPI0006") + Scope(\_GPE) { + Name(_HID, "ACPI0006") - Method(_L00) { - } - Method(_E01) { + Method(_L00) { + } + Method(_E01) { #if 0 - // PCI hotplug event - \_SB.PCI0.PCNF() + // PCI hotplug event + \_SB.PCI0.PCNF() #endif - } - Method(_E02) { + } + Method(_E02) { #if 0 - // CPU hotplug event - \_SB.PRSC() + // CPU hotplug event + \_SB.PRSC() #endif - } - Method(_L03) { - } - Method(_L04) { - } - Method(_L05) { - } - Method(_L06) { - } - Method(_L07) { - } - Method(_L08) { - } - Method(_L09) { - } - Method(_L0A) { - } - Method(_L0B) { - } - Method(_L0C) { - } - Method(_L0D) { - } - Method(_L0E) { - } - Method(_L0F) { - } - } + } + Method(_L03) { + } + Method(_L04) { + } + Method(_L05) { + } + Method(_L06) { + } + Method(_L07) { + } + Method(_L08) { + } + Method(_L09) { + } + Method(_L0A) { + } + Method(_L0B) { + } + Method(_L0C) { + } + Method(_L0D) { + } + Method(_L0E) { + } + Method(_L0F) { + } + } } diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 4e4e8095c4..e7aac4ce7b 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -19,93 +19,93 @@ */ DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision - "CORE", // OEMID - "COREBOOT", // TABLE ID - 0x2 // OEM Revision - ) + "dsdt.aml", // Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "CORE", // OEMID + "COREBOOT", // TABLE ID + 0x2 // OEM Revision + ) { #include "../qemu-i440fx/acpi/dbug.asl" - Scope(\_SB) { - OperationRegion(PCST, SystemIO, 0xae00, 0x0c) - OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) - Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { - PCIB, 8, - } - } + Scope(\_SB) { + OperationRegion(PCST, SystemIO, 0xae00, 0x0c) + OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) + Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { + PCIB, 8, + } + } /**************************************************************** * PCI Bus definition ****************************************************************/ - Scope(\_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A08")) - Name(_CID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - - // _OSC: based on sample of ACPI3.0b spec - Name(SUPP, 0) // PCI _OSC Support Field value - Name(CTRL, 0) // PCI _OSC Control Field value - Method(_OSC, 4) { - // Create DWORD-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 0, CDW1) - - // Check for proper UUID - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWORD-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 4, CDW2) - CreateDWordField(Arg3, 8, CDW3) - - // Save Capabilities DWORD2 & 3 - Store(CDW2, SUPP) - Store(CDW3, CTRL) - - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL, 0x1D, CTRL) + Scope(\_SB) { + Device(PCI0) { + Name(_HID, EisaId("PNP0A08")) + Name(_CID, EisaId("PNP0A03")) + Name(_ADR, 0x00) + Name(_UID, 1) + + // _OSC: based on sample of ACPI3.0b spec + Name(SUPP, 0) // PCI _OSC Support Field value + Name(CTRL, 0) // PCI _OSC Control Field value + Method(_OSC, 4) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 0, CDW1) + + // Check for proper UUID + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 4, CDW2) + CreateDWordField(Arg3, 8, CDW3) + + // Save Capabilities DWORD2 & 3 + Store(CDW2, SUPP) + Store(CDW3, CTRL) + + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL, 0x1D, CTRL) #if 0 // For now, nothing to do - If (Not(And(CDW1, 1))) { // Query flag clear? - // Disable GPEs for features granted native control. - If (And(CTRL, 0x01)) { // Hot plug control granted? - Store(0, HPCE) // clear the hot plug SCI enable bit - Store(1, HPCS) // clear the hot plug SCI status bit - } - If (And(CTRL, 0x04)) { // PME control granted? - Store(0, PMCE) // clear the PME SCI enable bit - Store(1, PMCS) // clear the PME SCI status bit - } - If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? - // Set status to not restore PCI Express cap structure - // upon resume from S3 - Store(1, S3CR) - } - } + If (Not(And(CDW1, 1))) { // Query flag clear? + // Disable GPEs for features granted native control. + If (And(CTRL, 0x01)) { // Hot plug control granted? + Store(0, HPCE) // clear the hot plug SCI enable bit + Store(1, HPCS) // clear the hot plug SCI status bit + } + If (And(CTRL, 0x04)) { // PME control granted? + Store(0, PMCE) // clear the PME SCI enable bit + Store(1, PMCS) // clear the PME SCI status bit + } + If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? + // Set status to not restore PCI Express cap structure + // upon resume from S3 + Store(1, S3CR) + } + } #endif - If (LNotEqual(Arg1, One)) { - // Unknown revision - Or(CDW1, 0x08, CDW1) - } - If (LNotEqual(CDW3, CTRL)) { - // Capabilities bits were masked - Or(CDW1, 0x10, CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL, CDW3) - } Else { - Or(CDW1, 4, CDW1) // Unrecognized UUID - } - Return (Arg3) - } - } - } + If (LNotEqual(Arg1, One)) { + // Unknown revision + Or(CDW1, 0x08, CDW1) + } + If (LNotEqual(CDW3, CTRL)) { + // Capabilities bits were masked + Or(CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL, CDW3) + } Else { + Or(CDW1, 4, CDW1) // Unrecognized UUID + } + Return (Arg3) + } + } + } #include "../qemu-i440fx/acpi/pci-crs.asl" #include "../qemu-i440fx/acpi/hpet.asl" @@ -115,55 +115,55 @@ DefinitionBlock ( * VGA ****************************************************************/ - Scope(\_SB.PCI0) { - Device(VGA) { - Name(_ADR, 0x00010000) - Method(_S1D, 0, NotSerialized) { - Return (0x00) - } - Method(_S2D, 0, NotSerialized) { - Return (0x00) - } - Method(_S3D, 0, NotSerialized) { - Return (0x00) - } - } - } + Scope(\_SB.PCI0) { + Device(VGA) { + Name(_ADR, 0x00010000) + Method(_S1D, 0, NotSerialized) { + Return (0x00) + } + Method(_S2D, 0, NotSerialized) { + Return (0x00) + } + Method(_S3D, 0, NotSerialized) { + Return (0x00) + } + } + } /**************************************************************** * LPC ISA bridge ****************************************************************/ - Scope(\_SB.PCI0) { - /* PCI D31:f0 LPC ISA bridge */ - Device(ISA) { - /* PCI D31:f0 */ - Name(_ADR, 0x001f0000) - - /* ICH9 PCI to ISA irq remapping */ - OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) - - OperationRegion(LPCD, PCI_Config, 0x80, 0x2) - Field(LPCD, AnyAcc, NoLock, Preserve) { - COMA, 3, - , 1, - COMB, 3, - - Offset(0x01), - LPTD, 2, - , 2, - FDCD, 2 - } - OperationRegion(LPCE, PCI_Config, 0x82, 0x2) - Field(LPCE, AnyAcc, NoLock, Preserve) { - CAEN, 1, - CBEN, 1, - LPEN, 1, - FDEN, 1 - } - } - } + Scope(\_SB.PCI0) { + /* PCI D31:f0 LPC ISA bridge */ + Device(ISA) { + /* PCI D31:f0 */ + Name(_ADR, 0x001f0000) + + /* ICH9 PCI to ISA irq remapping */ + OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) + + OperationRegion(LPCD, PCI_Config, 0x80, 0x2) + Field(LPCD, AnyAcc, NoLock, Preserve) { + COMA, 3, + , 1, + COMB, 3, + + Offset(0x01), + LPTD, 2, + , 2, + FDCD, 2 + } + OperationRegion(LPCE, PCI_Config, 0x82, 0x2) + Field(LPCE, AnyAcc, NoLock, Preserve) { + CAEN, 1, + CBEN, 1, + LPEN, 1, + FDEN, 1 + } + } + } #include "../qemu-i440fx/acpi/isa.asl" @@ -172,19 +172,19 @@ DefinitionBlock ( * PCI IRQs ****************************************************************/ - /* Zero => PIC mode, One => APIC Mode */ - Name(\PICF, Zero) - Method(\_PIC, 1, NotSerialized) { - Store(Arg0, \PICF) - } + /* Zero => PIC mode, One => APIC Mode */ + Name(\PICF, Zero) + Method(\_PIC, 1, NotSerialized) { + Store(Arg0, \PICF) + } - Scope(\_SB) { - Scope(PCI0) { + Scope(\_SB) { + Scope(PCI0) { #define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \ - Package() { nr##ffff, 0, lnk0, 0 }, \ - Package() { nr##ffff, 1, lnk1, 0 }, \ - Package() { nr##ffff, 2, lnk2, 0 }, \ - Package() { nr##ffff, 3, lnk3, 0 } + Package() { nr##ffff, 0, lnk0, 0 }, \ + Package() { nr##ffff, 1, lnk1, 0 }, \ + Package() { nr##ffff, 2, lnk2, 0 }, \ + Package() { nr##ffff, 3, lnk3, 0 } #define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD) #define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA) @@ -196,52 +196,52 @@ DefinitionBlock ( #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) - Name(PRTP, Package() { - prt_slot_lnkE(0x0000), - prt_slot_lnkF(0x0001), - prt_slot_lnkG(0x0002), - prt_slot_lnkH(0x0003), - prt_slot_lnkE(0x0004), - prt_slot_lnkF(0x0005), - prt_slot_lnkG(0x0006), - prt_slot_lnkH(0x0007), - prt_slot_lnkE(0x0008), - prt_slot_lnkF(0x0009), - prt_slot_lnkG(0x000a), - prt_slot_lnkH(0x000b), - prt_slot_lnkE(0x000c), - prt_slot_lnkF(0x000d), - prt_slot_lnkG(0x000e), - prt_slot_lnkH(0x000f), - prt_slot_lnkE(0x0010), - prt_slot_lnkF(0x0011), - prt_slot_lnkG(0x0012), - prt_slot_lnkH(0x0013), - prt_slot_lnkE(0x0014), - prt_slot_lnkF(0x0015), - prt_slot_lnkG(0x0016), - prt_slot_lnkH(0x0017), - prt_slot_lnkE(0x0018), - - /* INTA -> PIRQA for slot 25 - 31 - see the default value of D<N>IR */ - prt_slot_lnkA(0x0019), - prt_slot_lnkA(0x001a), - prt_slot_lnkA(0x001b), - prt_slot_lnkA(0x001c), - prt_slot_lnkA(0x001d), - - /* PCIe->PCI bridge. use PIRQ[E-H] */ - prt_slot_lnkE(0x001e), - - prt_slot_lnkA(0x001f) - }) + Name(PRTP, Package() { + prt_slot_lnkE(0x0000), + prt_slot_lnkF(0x0001), + prt_slot_lnkG(0x0002), + prt_slot_lnkH(0x0003), + prt_slot_lnkE(0x0004), + prt_slot_lnkF(0x0005), + prt_slot_lnkG(0x0006), + prt_slot_lnkH(0x0007), + prt_slot_lnkE(0x0008), + prt_slot_lnkF(0x0009), + prt_slot_lnkG(0x000a), + prt_slot_lnkH(0x000b), + prt_slot_lnkE(0x000c), + prt_slot_lnkF(0x000d), + prt_slot_lnkG(0x000e), + prt_slot_lnkH(0x000f), + prt_slot_lnkE(0x0010), + prt_slot_lnkF(0x0011), + prt_slot_lnkG(0x0012), + prt_slot_lnkH(0x0013), + prt_slot_lnkE(0x0014), + prt_slot_lnkF(0x0015), + prt_slot_lnkG(0x0016), + prt_slot_lnkH(0x0017), + prt_slot_lnkE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31 + see the default value of D<N>IR */ + prt_slot_lnkA(0x0019), + prt_slot_lnkA(0x001a), + prt_slot_lnkA(0x001b), + prt_slot_lnkA(0x001c), + prt_slot_lnkA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_lnkE(0x001e), + + prt_slot_lnkA(0x001f) + }) #define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ - Package() { nr##ffff, 0, gsi0, 0 }, \ - Package() { nr##ffff, 1, gsi1, 0 }, \ - Package() { nr##ffff, 2, gsi2, 0 }, \ - Package() { nr##ffff, 3, gsi3, 0 } + Package() { nr##ffff, 0, gsi0, 0 }, \ + Package() { nr##ffff, 1, gsi1, 0 }, \ + Package() { nr##ffff, 2, gsi2, 0 }, \ + Package() { nr##ffff, 3, gsi3, 0 } #define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) @@ -253,150 +253,150 @@ DefinitionBlock ( #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG) - Name(PRTA, Package() { - prt_slot_gsiE(0x0000), - prt_slot_gsiF(0x0001), - prt_slot_gsiG(0x0002), - prt_slot_gsiH(0x0003), - prt_slot_gsiE(0x0004), - prt_slot_gsiF(0x0005), - prt_slot_gsiG(0x0006), - prt_slot_gsiH(0x0007), - prt_slot_gsiE(0x0008), - prt_slot_gsiF(0x0009), - prt_slot_gsiG(0x000a), - prt_slot_gsiH(0x000b), - prt_slot_gsiE(0x000c), - prt_slot_gsiF(0x000d), - prt_slot_gsiG(0x000e), - prt_slot_gsiH(0x000f), - prt_slot_gsiE(0x0010), - prt_slot_gsiF(0x0011), - prt_slot_gsiG(0x0012), - prt_slot_gsiH(0x0013), - prt_slot_gsiE(0x0014), - prt_slot_gsiF(0x0015), - prt_slot_gsiG(0x0016), - prt_slot_gsiH(0x0017), - prt_slot_gsiE(0x0018), - - /* INTA -> PIRQA for slot 25 - 31, but 30 - see the default value of D<N>IR */ - prt_slot_gsiA(0x0019), - prt_slot_gsiA(0x001a), - prt_slot_gsiA(0x001b), - prt_slot_gsiA(0x001c), - prt_slot_gsiA(0x001d), - - /* PCIe->PCI bridge. use PIRQ[E-H] */ - prt_slot_gsiE(0x001e), - - prt_slot_gsiA(0x001f) - }) - - Method(_PRT, 0, NotSerialized) { - /* PCI IRQ routing table, example from ACPI 2.0a specification, - section 6.2.8.1 */ - /* Note: we provide the same info as the PCI routing - table of the Bochs BIOS */ - If (LEqual(\PICF, Zero)) { - Return (PRTP) - } Else { - Return (PRTA) - } - } - } - - Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { - PRQA, 8, - PRQB, 8, - PRQC, 8, - PRQD, 8, - - Offset(0x08), - PRQE, 8, - PRQF, 8, - PRQG, 8, - PRQH, 8 - } - - Method(IQST, 1, NotSerialized) { - // _STA method - get status - If (And(0x80, Arg0)) { - Return (0x09) - } - Return (0x0B) - } - Method(IQCR, 1, Serialized) { - // _CRS method - get current settings - Name(PRR0, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 0 } - }) - CreateDWordField(PRR0, 0x05, PRRI) - Store(And(Arg0, 0x0F), PRRI) - Return (PRR0) - } + Name(PRTA, Package() { + prt_slot_gsiE(0x0000), + prt_slot_gsiF(0x0001), + prt_slot_gsiG(0x0002), + prt_slot_gsiH(0x0003), + prt_slot_gsiE(0x0004), + prt_slot_gsiF(0x0005), + prt_slot_gsiG(0x0006), + prt_slot_gsiH(0x0007), + prt_slot_gsiE(0x0008), + prt_slot_gsiF(0x0009), + prt_slot_gsiG(0x000a), + prt_slot_gsiH(0x000b), + prt_slot_gsiE(0x000c), + prt_slot_gsiF(0x000d), + prt_slot_gsiG(0x000e), + prt_slot_gsiH(0x000f), + prt_slot_gsiE(0x0010), + prt_slot_gsiF(0x0011), + prt_slot_gsiG(0x0012), + prt_slot_gsiH(0x0013), + prt_slot_gsiE(0x0014), + prt_slot_gsiF(0x0015), + prt_slot_gsiG(0x0016), + prt_slot_gsiH(0x0017), + prt_slot_gsiE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31, but 30 + see the default value of D<N>IR */ + prt_slot_gsiA(0x0019), + prt_slot_gsiA(0x001a), + prt_slot_gsiA(0x001b), + prt_slot_gsiA(0x001c), + prt_slot_gsiA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_gsiE(0x001e), + + prt_slot_gsiA(0x001f) + }) + + Method(_PRT, 0, NotSerialized) { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ + If (LEqual(\PICF, Zero)) { + Return (PRTP) + } Else { + Return (PRTA) + } + } + } + + Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + + Offset(0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method(IQST, 1, NotSerialized) { + // _STA method - get status + If (And(0x80, Arg0)) { + Return (0x09) + } + Return (0x0B) + } + Method(IQCR, 1, Serialized) { + // _CRS method - get current settings + Name(PRR0, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 0 } + }) + CreateDWordField(PRR0, 0x05, PRRI) + Store(And(Arg0, 0x0F), PRRI) + Return (PRR0) + } #define define_link(link, uid, reg) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - 5, 10, 11 \ - } \ - }) \ - Method(_STA, 0, NotSerialized) { \ - Return (IQST(reg)) \ - } \ - Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ - } \ - Method(_CRS, 0, NotSerialized) { \ - Return (IQCR(reg)) \ - } \ - Method(_SRS, 1, NotSerialized) { \ - CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ - } \ - } - - define_link(LNKA, 0, PRQA) - define_link(LNKB, 1, PRQB) - define_link(LNKC, 2, PRQC) - define_link(LNKD, 3, PRQD) - define_link(LNKE, 4, PRQE) - define_link(LNKF, 5, PRQF) - define_link(LNKG, 6, PRQG) - define_link(LNKH, 7, PRQH) + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + 5, 10, 11 \ + } \ + }) \ + Method(_STA, 0, NotSerialized) { \ + Return (IQST(reg)) \ + } \ + Method(_DIS, 0, NotSerialized) { \ + Or(reg, 0x80, reg) \ + } \ + Method(_CRS, 0, NotSerialized) { \ + Return (IQCR(reg)) \ + } \ + Method(_SRS, 1, NotSerialized) { \ + CreateDWordField(Arg0, 0x05, PRRI) \ + Store(PRRI, reg) \ + } \ + } + + define_link(LNKA, 0, PRQA) + define_link(LNKB, 1, PRQB) + define_link(LNKC, 2, PRQC) + define_link(LNKD, 3, PRQD) + define_link(LNKE, 4, PRQE) + define_link(LNKF, 5, PRQF) + define_link(LNKG, 6, PRQG) + define_link(LNKH, 7, PRQH) #define define_gsi_link(link, uid, gsi) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - gsi \ - } \ - }) \ - Name(_CRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - gsi \ - } \ - }) \ - Method(_SRS, 1, NotSerialized) { \ - } \ - } - - define_gsi_link(GSIA, 0, 0x10) - define_gsi_link(GSIB, 0, 0x11) - define_gsi_link(GSIC, 0, 0x12) - define_gsi_link(GSID, 0, 0x13) - define_gsi_link(GSIE, 0, 0x14) - define_gsi_link(GSIF, 0, 0x15) - define_gsi_link(GSIG, 0, 0x16) - define_gsi_link(GSIH, 0, 0x17) - } + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Name(_CRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Method(_SRS, 1, NotSerialized) { \ + } \ + } + + define_gsi_link(GSIA, 0, 0x10) + define_gsi_link(GSIB, 0, 0x11) + define_gsi_link(GSIC, 0, 0x12) + define_gsi_link(GSID, 0, 0x13) + define_gsi_link(GSIE, 0, 0x14) + define_gsi_link(GSIF, 0, 0x15) + define_gsi_link(GSIG, 0, 0x16) + define_gsi_link(GSIH, 0, 0x17) + } #if 0 #include "../qemu-i440fx/acpi/cpu-hotplug.asl" @@ -407,44 +407,44 @@ DefinitionBlock ( * General purpose events ****************************************************************/ - Scope(\_GPE) { - Name(_HID, "ACPI0006") + Scope(\_GPE) { + Name(_HID, "ACPI0006") - Method(_L00) { - } - Method(_L01) { + Method(_L00) { + } + Method(_L01) { #if 0 - // CPU hotplug event - \_SB.PRSC() + // CPU hotplug event + \_SB.PRSC() #endif - } - Method(_L02) { - } - Method(_L03) { - } - Method(_L04) { - } - Method(_L05) { - } - Method(_L06) { - } - Method(_L07) { - } - Method(_L08) { - } - Method(_L09) { - } - Method(_L0A) { - } - Method(_L0B) { - } - Method(_L0C) { - } - Method(_L0D) { - } - Method(_L0E) { - } - Method(_L0F) { - } - } + } + Method(_L02) { + } + Method(_L03) { + } + Method(_L04) { + } + Method(_L05) { + } + Method(_L06) { + } + Method(_L07) { + } + Method(_L08) { + } + Method(_L09) { + } + Method(_L0A) { + } + Method(_L0B) { + } + Method(_L0C) { + } + Method(_L0D) { + } + Method(_L0E) { + } + Method(_L0F) { + } + } } diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl index e0e8dfb382..c53f36a47e 100644 --- a/src/mainboard/gigabyte/m57sli/dsdt.asl +++ b/src/mainboard/gigabyte/m57sli/dsdt.asl @@ -51,7 +51,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) External (HCDN) Method (_CRS, 0, NotSerialized) - { + { Name (BUF0, ResourceTemplate () { IO (Decode16, diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index 59af6ddb95..29ea7d6336 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -37,7 +37,7 @@ DefinitionBlock( Device (PCI0) { #include <acpi/southcluster.asl> - #include <acpi/dptf/cpu.asl> + #include <acpi/dptf/cpu.asl> } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/iwill/dk8_htx/dsdt.asl b/src/mainboard/iwill/dk8_htx/dsdt.asl index 51a4a38dc6..9a2f570109 100644 --- a/src/mainboard/iwill/dk8_htx/dsdt.asl +++ b/src/mainboard/iwill/dk8_htx/dsdt.asl @@ -3,26 +3,26 @@ */ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) { - Scope (_PR) - { - Processor (CPU0, 0x00, 0x0000C010, 0x06) {} - Processor (CPU1, 0x01, 0x00000000, 0x00) {} - Processor (CPU2, 0x02, 0x00000000, 0x00) {} - Processor (CPU3, 0x03, 0x00000000, 0x00) {} - - } - - Method (FWSO, 0, NotSerialized) { } - - Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) - Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 }) - Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 }) - Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 }) - - Scope (_SB) - { - Device (PCI0) - { + Scope (_PR) + { + Processor (CPU0, 0x00, 0x0000C010, 0x06) {} + Processor (CPU1, 0x01, 0x00000000, 0x00) {} + Processor (CPU2, 0x02, 0x00000000, 0x00) {} + Processor (CPU3, 0x03, 0x00000000, 0x00) {} + + } + + Method (FWSO, 0, NotSerialized) { } + + Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) + Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 }) + Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 }) + Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 }) + + Scope (_SB) + { + Device (PCI0) + { /* BUS0 root bus */ External (BUSN) @@ -36,176 +36,176 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (CBST) - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - \_SB.OSVR () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci0_hc.asl" - - } - Device (PCI1) - { - Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.CBST) - } - Name (_BBN, 0x00) - } - - - } - - Scope (_GPE) - { - Method (_L08, 0, NotSerialized) - { - Notify (\_SB.PCI0, 0x02) //PME# Wakeup - } - - Method (_L0F, 0, NotSerialized) - { - Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - } - - Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B - { - Notify (\_SB.PCI0.PG0B, 0x02) - } - - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A - { - Notify (\_SB.PCI0.PG0A, 0x02) - } - } - - Method (_PTS, 1, NotSerialized) - { - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG1) - } + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x000CFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00010000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + \_SB.OSVR () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci0_hc.asl" + + } + Device (PCI1) + { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00000000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + Return (\_SB.PCI0.CBST) + } + Name (_BBN, 0x00) + } + + + } + + Scope (_GPE) + { + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0, 0x02) //PME# Wakeup + } + + Method (_L0F, 0, NotSerialized) + { + Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + } + + Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B + { + Notify (\_SB.PCI0.PG0B, 0x02) + } + + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + { + Notify (\_SB.PCI0.PG0A, 0x02) + } + } + + Method (_PTS, 1, NotSerialized) + { + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) + } /* - Method (_WAK, 1, NotSerialized) - { - Or (Arg0, 0xE0, Local0) - Store (Local0, DBG1) - } + Method (_WAK, 1, NotSerialized) + { + Or (Arg0, 0xE0, Local0) + Store (Local0, DBG1) + } */ - Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode - Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method - { - Store (Arg0, PICF) - } - - OperationRegion (DEBG, SystemIO, 0x80, 0x01) - Field (DEBG, ByteAcc, Lock, Preserve) - { - DBG1, 8 - } - - OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) - Field (EXTM, WordAcc, Lock, Preserve) - { - AMEM, 32 - } - - OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) - Field (VGAM, ByteAcc, Lock, Preserve) - { - VGA1, 8 - } - - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } - - OperationRegion (GSTS, SystemIO, 0xC028, 0x02) - Field (GSTS, ByteAcc, NoLock, Preserve) - { - , 4, - IRQR, 1 - } - - OperationRegion (Z007, SystemIO, 0x21, 0x01) - Field (Z007, ByteAcc, NoLock, Preserve) - { - Z008, 8 - } - - OperationRegion (Z009, SystemIO, 0xA1, 0x01) - Field (Z009, ByteAcc, NoLock, Preserve) - { - Z00A, 8 - } - - #include "northbridge/amd/amdk8/util.asl" + Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode + Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method + { + Store (Arg0, PICF) + } + + OperationRegion (DEBG, SystemIO, 0x80, 0x01) + Field (DEBG, ByteAcc, Lock, Preserve) + { + DBG1, 8 + } + + OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) + Field (EXTM, WordAcc, Lock, Preserve) + { + AMEM, 32 + } + + OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) + Field (VGAM, ByteAcc, Lock, Preserve) + { + VGA1, 8 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + OperationRegion (GSTS, SystemIO, 0xC028, 0x02) + Field (GSTS, ByteAcc, NoLock, Preserve) + { + , 4, + IRQR, 1 + } + + OperationRegion (Z007, SystemIO, 0x21, 0x01) + Field (Z007, ByteAcc, NoLock, Preserve) + { + Z008, 8 + } + + OperationRegion (Z009, SystemIO, 0xA1, 0x01) + Field (Z009, ByteAcc, NoLock, Preserve) + { + Z00A, 8 + } + + #include "northbridge/amd/amdk8/util.asl" } diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 19096fda08..9ee2dd1b0e 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -90,7 +90,7 @@ DefinitionBlock( */ Scope (\_SB.PCI0.LPCB) { - #include <drivers/pc80/tpm/acpi/tpm.asl> + #include <drivers/pc80/tpm/acpi/tpm.asl> } /* Chipset specific sleep states */ diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index 723174e56f..4f1009af46 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -49,7 +49,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) External (HCDN) Method (_CRS, 0, NotSerialized) - { + { Name (BUF0, ResourceTemplate () { IO (Decode16, diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 3d85966630..6cf137f832 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -396,48 +396,48 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Return(0x0B) /* Status is visible */ } - Device (MEMR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (MEM1, ResourceTemplate () - { - Memory32Fixed (ReadWrite, - 0x00000000, // Address Base - 0x00000000, // Address Length - _Y1A) - Memory32Fixed (ReadWrite, - 0x00000000, // Address Base - 0x00000000, // Address Length - _Y1B) - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01) - CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01) - CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02) - CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02) - If (PCIF) - { - Store (IO_APIC_ADDR, MB01) - Store (LOCAL_APIC_ADDR, MB02) - Store (0x1000, ML01) - Store (0x1000, ML02) - } - - Return (MEM1) - } - } + Device (MEMR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (MEM1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000000, // Address Length + _Y1A) + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000000, // Address Length + _Y1B) + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01) + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01) + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02) + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02) + If (PCIF) + { + Store (IO_APIC_ADDR, MB01) + Store (LOCAL_APIC_ADDR, MB02) + Store (0x1000, ML01) + Store (0x1000, ML02) + } + + Return (MEM1) + } + } Method(_PRT,0) { If(PCIF){ Return(APR0) } /* APIC mode */ Return (PR0) /* PIC Mode */ } /* end _PRT */ - OperationRegion (BAR1, PCI_Config, 0x14, 0x04) - Field (BAR1, ByteAcc, NoLock, Preserve) - { - Z009, 32 - } + OperationRegion (BAR1, PCI_Config, 0x14, 0x04) + Field (BAR1, ByteAcc, NoLock, Preserve) + { + Z009, 32 + } /* Describe the Northbridge devices */ Device(AMRT) { @@ -451,8 +451,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Method(_PRT,0) { Return (APR1) } Device (VGA) - { - Name (_ADR, 0x00050000) + { + Name (_ADR, 0x00050000) Method (_DOS, 1) { /* Windows 2000 and Windows XP call _DOS to enable/disable @@ -461,11 +461,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) */ Store (And(Arg0, 7), DSEN) } - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - } + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } } /* end AGPB */ /* The external GFX bridge */ @@ -610,8 +610,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Device(LPC0) { - Name (_ADR, 0x00140003) - Mutex (PSMX, 0x00) + Name (_ADR, 0x00140003) + Mutex (PSMX, 0x00) /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) @@ -959,7 +959,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Device(TMR) { /* Timer */ Name(_HID,EISAID("PNP0100")) /* System Timer */ Name(_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive, ) {0} + IRQ (Edge, ActiveHigh, Exclusive, ) {0} IO(Decode16, 0x0040, 0x0040, 1, 4) /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ }) @@ -1015,55 +1015,55 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Method(_CRS, 0) { Return(CRS) } - } - - Device (KBC0) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0060, // Range Minimum - 0x0060, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IO (Decode16, - 0x0064, // Range Minimum - 0x0064, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IRQ (Edge, ActiveHigh, Exclusive, ) {1} - }) } - Device (MSE0) - { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () - { - IRQ (Edge, ActiveHigh, Exclusive, ) {12} - }) + Device (KBC0) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) {1} + }) + } + + Device (MSE0) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQ (Edge, ActiveHigh, Exclusive, ) {12} + }) } } /* end LPC0 */ Device(ACAD) { Name(_ADR, 0x00140005) Name (_PRW, Package (0x02) - { - 0x0C, - 0x04 - }) + { + 0x0C, + 0x04 + }) } /* end Ac97audio */ Device(ACMD) { Name(_ADR, 0x00140006) Name (_PRW, Package (0x02) - { - 0x0C, - 0x04 - }) + { + 0x0C, + 0x04 + }) } /* end Ac97modem */ /* ITE IT8712F Support */ diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 8395c7b26b..9106b83196 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1551,18 +1551,18 @@ DefinitionBlock ( CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, BAS1) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, LEN1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) //DBGO(TOM1) Return (CRS) diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 84788b8c70..0a8cbdda83 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -1567,18 +1567,18 @@ DefinitionBlock ( CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, BAS1) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, LEN1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) //DBGO(TOM1) Return (CRS) diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index 015687e215..56471e3509 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -1551,18 +1551,18 @@ DefinitionBlock ( CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, BAS1) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, LEN1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) //DBGO(TOM1) Return (CRS) diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index c4743ee102..473bc851be 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -43,7 +43,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) /* Root of the bus hierarchy */ Scope (\_SB) - { + { /* Define how interrupt Link A is plumbed in */ Device (LNKA) { @@ -54,7 +54,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Method (_STA, 0, NotSerialized) { Return (0x0B) - } + } /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) @@ -71,19 +71,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs - * we are using for PCI - only here to keep Linux ACPI + * we are using for PCI - only here to keep Linux ACPI * happy */ Method (_PRS, 0, NotSerialized) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + }) If (LNot (PICF)) { Return (PRSP) @@ -91,9 +91,9 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) } - } + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -113,7 +113,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Method (_STA, 0, NotSerialized) { Return (0x0B) - } + } /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) @@ -130,19 +130,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs - * we are using for PCI - only here to keep Linux ACPI + * we are using for PCI - only here to keep Linux ACPI * happy */ Method (_PRS, 0, NotSerialized) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + }) If (LNot (PICF)) { Return (PRSP) @@ -150,10 +150,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) } - } + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -173,7 +173,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Method (_STA, 0, NotSerialized) { Return (0x0B) - } + } /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) @@ -190,19 +190,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs - * we are using for PCI - only here to keep Linux ACPI + * we are using for PCI - only here to keep Linux ACPI * happy */ Method (_PRS, 0, NotSerialized) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + }) If (LNot (PICF)) { Return (PRSP) @@ -210,10 +210,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) } - } + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -233,7 +233,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Method (_STA, 0, NotSerialized) { Return (0x0B) - } + } /* Current Resources - return irq set up in BIOS */ Method (_CRS, 0, NotSerialized) @@ -250,19 +250,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs - * we are using for PCI - only here to keep Linux ACPI + * we are using for PCI - only here to keep Linux ACPI * happy */ Method (_PRS, 0, NotSerialized) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + }) If (LNot (PICF)) { Return (PRSP) @@ -270,10 +270,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) } - } + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -296,17 +296,17 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) #include "acpi/irq.asl" /* PCI Routing Table */ - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) - { - Return (PICM) - } - Else - { - Return (APIC) - } - } + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) + { + Return (PICM) + } + Else + { + Return (APIC) + } + } Device (P2PB) /* PCI to PCI bridge */ { |