Replace hlt() loops with halt()

Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

15 files changed, 38 insertions, 41 deletions

diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index c137b146f9..0d55e532f0 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
@@ -71,10 +72,7 @@ void soft_reset(void)
 	tmp |= 0x01;
 	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 
-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }
 
 #include "southbridge/via/k8t890/early_car.c"
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 5c78ab1a0a..3ed2491737 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
@@ -71,10 +72,7 @@ void soft_reset(void)
 	tmp |= 0x01;
 	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 
-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }
 
 #include "southbridge/via/k8t890/early_car.c"
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 15b86828d6..dab3193d70 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -33,6 +33,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
@@ -69,10 +70,7 @@ void soft_reset(void)
 	tmp |= 0x01;
 	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 
-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }
 
 #include "southbridge/via/k8t890/early_car.c"
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index adcdfc796f..42b03c8a7a 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -99,10 +100,7 @@ void soft_reset(void)
 	/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
 	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 
-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }
 
 unsigned int get_sbdn(unsigned bus)
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 30ba4682d8..f776351d14 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -34,6 +34,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
+#include <halt.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -83,10 +84,7 @@ void soft_reset(void)
 	/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
 	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 
-	while (1) {
-		/* daisy daisy ... */
-		hlt();
-	}
+	halt();
 }
 
 unsigned int get_sbdn(unsigned bus)
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
index e7933d5ea9..d43df8d02c 100644
--- a/src/mainboard/dmp/vortex86ex/romstage.c
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -23,6 +23,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
+#include <halt.h>
 #include "drivers/pc80/i8254.c"
 #include "northbridge/dmp/vortex86ex/northbridge.h"
 #include "southbridge/dmp/vortex86ex/southbridge.h"
@@ -309,8 +310,7 @@ static void main(unsigned long bist)
 	if (dmp_id != DMP_CPUID_EX) {
 		/* Not DMP Vortex86EX CPU. */
 		post_code(POST_DMP_ID_ERR);
-		while (1)
-			hlt();
+		halt();
 	}
 	disable_watchdog();
 	set_ex_powerdown_control();
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 80c0742985..6cf86ada5a 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -38,6 +38,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -151,7 +152,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -193,7 +194,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index f90d7e7728..f58ab1359c 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -40,6 +40,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -191,7 +192,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -241,7 +242,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index c25b419389..69711d9203 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -38,6 +38,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -150,7 +151,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -192,7 +193,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 6290e03165..e8f2927526 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -38,6 +38,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 #include <bootmode.h>
 #if CONFIG_CHROMEOS
@@ -196,7 +197,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 
@@ -246,7 +247,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 9ac70ef78d..c90ece2e56 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -31,6 +31,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <halt.h>
 #include <reset.h>
 #include "superio/smsc/sio1007/chip.h"
 #include <fsp_util.h>
@@ -49,9 +50,7 @@
 static inline void reset_system(void)
 {
 	hard_reset();
-	while (1) {
-		hlt();
-	}
+	halt();
 }
 
 static void pch_enable_lpc(void)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index d50093e08d..76edf7fd0d 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -38,6 +38,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -203,7 +204,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -249,7 +250,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index bfe7715826..6926952e8c 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -37,6 +37,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 
 static void pch_enable_lpc(void)
@@ -190,7 +191,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -237,7 +238,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 6595f0d3dd..5b8646a1ce 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -40,6 +40,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "option_table.h"
 #include "gpio.h"
 #if CONFIG_DRIVERS_UART_8250IO
@@ -180,7 +181,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -270,7 +271,7 @@ void main(unsigned long bist)
 	if (boot_mode == 2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 	post_code(0x3f);
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 2c651ae799..f842ad2e49 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -41,6 +41,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
 #include "gpio.h"
 #if CONFIG_DRIVERS_UART_8250IO
 #include "superio/smsc/lpc47n207/lpc47n207.h"
@@ -218,7 +219,7 @@ void main(unsigned long bist)
 		/* System is not happy after keyboard reset... */
 		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
@@ -279,7 +280,7 @@ void main(unsigned long bist)
 	if (boot_mode==2 && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 	northbridge_romstage_finalize(boot_mode==2);