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authorMathew King <mathewk@chromium.org>2019-10-14 12:07:23 -0600
committerDuncan Laurie <dlaurie@chromium.org>2019-12-02 23:28:16 +0000
commitc487ac1a9fea07023ca3a8e95b8f44eb67a9a01d (patch)
treedcd67799be537a5ccd5959ef10a5dcf2317a75ca /src/mainboard
parentc650e130ced0ee1f62fe0d9bff7a89b8717f6f28 (diff)
downloadcoreboot-c487ac1a9fea07023ca3a8e95b8f44eb67a9a01d.tar.xz
mb/g/drallion: Enable privacy screen on Drallion variant
Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system. BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36045 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/drallion/Kconfig1
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb16
-rw-r--r--src/mainboard/google/drallion/variants/drallion/include/variant/ec.h3
3 files changed, 19 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index accb9c8483..27818c091d 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -2,6 +2,7 @@
config BOARD_GOOGLE_BASEBOARD_DRALLION
def_bool n
select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_GENERIC_GFX
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_INTEL_ISH
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 6ecb689790..4c5cff25a0 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -224,7 +224,21 @@ chip soc/intel/cannonlake
end
device domain 0 on
device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
+ device pci 02.0 on
+ chip drivers/generic/gfx
+ register "device_count" = "1"
+ register "device[0].name" = ""LCD""
+ # Address is set following the ACPI spec section A.3.2
+ # for an internal panel on the first port of the graphics chip
+ register "device[0].addr" = "0x80010400"
+ register "device[0].privacy.enabled" = "1"
+ register "device[0].privacy.detect_function" = ""\\_SB.PCI0.LPCB.EC0.GPVD""
+ register "device[0].privacy.status_function" = ""\\_SB.PCI0.LPCB.EC0.GPVX""
+ register "device[0].privacy.enable_function" = ""\\_SB.PCI0.LPCB.EC0.EPVX""
+ register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX""
+ device generic 0 on end
+ end
+ end # Integrated Graphics Device
device pci 04.0 on end # SA Thermal device
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h
index 01a17b5f99..11e3be8404 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h
@@ -31,4 +31,7 @@
/* Enable DPTF */
#define EC_ENABLE_DPTF
+/* Enable privacy screen functionality */
+#define EC_ENABLE_PRIVACY
+
#endif