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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-06-04 00:11:03 -0500
committerRonald G. Minnich <rminnich@gmail.com>2015-11-11 06:14:20 +0100
commitdf1fb9c05f822b5a84c802617d3bad7d049dcd76 (patch)
treeeb4fc73a5365d91f4702b15342d67581eed0a0e6 /src/mainboard
parent1b708656b2f347ab05bd89643322f86b7110a814 (diff)
downloadcoreboot-df1fb9c05f822b5a84c802617d3bad7d049dcd76.tar.xz
amd/amdmct/mct_ddr3: Use training values from previous boot if possible
DRAM training accounts for most of the romstage startup time, yet if the hardware configuration has not changed from the previous boot the previously discovered training values are still valid. Use them if the DIMM configuration has not changed since the last boot. The SPD values of all installed DIMMs are hashed and stored in the S3 resume data area of the main system Flash device. If a DIMM is changed the hash will almost certainly change as well, forcing retraining on next boot. Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11976 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asus/kgpe-d16/cmos.layout1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout
index 264c893a76..b64a85b2a7 100644
--- a/src/mainboard/asus/kgpe-d16/cmos.layout
+++ b/src/mainboard/asus/kgpe-d16/cmos.layout
@@ -38,6 +38,7 @@ entries
458 4 e 11 hypertransport_speed_limit
462 2 e 12 minimum_memory_voltage
464 1 e 2 compute_unit_siblings
+465 1 r 0 allow_spd_nvram_cache_restore
477 1 e 1 ieee1394_controller
728 256 h 0 user_data
984 16 h 0 check_sum