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authorAndrey Petrov <anpetrov@fb.com>2020-04-30 12:47:25 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-05-01 23:11:38 +0000
commitf8f9b282b4f7ce2f6b83005db0f9aa5cf3f810ec (patch)
tree4924947c29c3693aea1e7e608cf6412ee225d2b5 /src/mainboard
parent8fb221dbd5ce11d27616a36eb6d5dc38bec7fd45 (diff)
downloadcoreboot-f8f9b282b4f7ce2f6b83005db0f9aa5cf3f810ec.tar.xz
mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/cedarisland_crb/romstage.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c
index 94af1b6dfe..0d1ccabfea 100644
--- a/src/mainboard/intel/cedarisland_crb/romstage.c
+++ b/src/mainboard/intel/cedarisland_crb/romstage.c
@@ -1,8 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
+#include <arch/mmio.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ void *start = (void *) m_cfg;
+
+ // BoardId
+ write8(start + 140, 0x1d);
+
+ // BoardTypeBitmask
+ write32(start + 104, 0x11111111);
+
+ // DebugPrintLevel
+ write8(start + 45, 8);
+
+ // KtiLinkSpeedMode
+ write8(start + 64, 0);
+
+ // KtiPrefetchEn
+ write8(start + 53, 2);
}