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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-27 23:45:20 +0100 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-28 00:00:30 +0100 |
| commit | fd611f9c2c8c751069c6cd1634a3e3e523ff098b (patch) | |
| tree | 3e1d3d844987a6f02d406e13f68aa37e3f55ec7e /src/mainboard | |
| parent | 9c29cfae8cc6214478a0a555e6901779eb19ef54 (diff) | |
| download | coreboot-fd611f9c2c8c751069c6cd1634a3e3e523ff098b.tar.xz | |
Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.
Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/northbridge.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/snow/ramstage.c | 5 |
2 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 3e7fbb99dd..d785bebbc4 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -9,10 +9,7 @@ #include <string.h> #include <delay.h> #include <smbios.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif #include "memory.c" @@ -38,11 +35,9 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif assign_resources(dev->link_list); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index a3e9236ac5..5970357512 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -18,10 +18,7 @@ */ #include <console/console.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif void hardwaremain(int boot_complete); void main(void) @@ -29,13 +26,11 @@ void main(void) console_init(); printk(BIOS_INFO, "hello from ramstage\n"); -#if CONFIG_WRITE_HIGH_TABLES /* place at top of physical memory */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; high_tables_base = CONFIG_SYS_SDRAM_BASE + ((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) - CONFIG_COREBOOT_TABLES_SIZE; -#endif hardwaremain(0); } |